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Configurable CDV system based on UVM for Analog Mixed-Signal Designs

IP.com Disclosure Number: IPCOM000234046D
Publication Date: 2014-Jan-08
Document File: 5 page(s) / 173K

Publishing Venue

The IP.com Prior Art Database

Abstract

Analog Mixed Signal (AMS) designs play a more and more important part in current IC designs. At the same time, this requires additional verification efforts over verifying a digital design due to below reasons: 1: For digital designs, driving 1 or 0 on a signal is enough. For an analog signal, different real values need to be driven. Furthermore, different analog signals might be driven with different values. 2: AMS designs (take ADC as an example) may have different channels, accuracy, and value range, etc. Developing a configurable verification system to suit different kinds of AMS designs shortens the verification cycle time. 3: Coverage is a metric used to measure the completeness of verifying a design. However, coverage for analog designs cannot be reported easily just like the digital parts. And also, cross coverage between two or more coverage points are important to measure the quality of the verification. In current verification flow, some dedicated values are driven on the ADC channel and then the conversion result is checked. There are three disadvantages on this: 1: The ADC with a high accuracy, mountains of dedicated values need to driven on one channel to check the design. Furthermore, driving multiple channels with different values results in exponential growth on the stimulus numbers, even so, some corner values still might be loss. 2: Parametric design is developed to increase the configuration for different chips, but it is not easy to develop the stimulus automatically for the parametric designs. Some manual updates are needed for different designs use different configurations. 3: No coverage reports to ensure the whole range is covered.

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Configurable CDV system based on UVM for Analog Mixed-Signal Designs

Introduction

Analog Mixed Signal (AMS) designs play a more and more important part in current IC designs. At the same time, this requires additional verification efforts over verifying a digital design due to below reasons:

1: For digital designs, driving 1 or 0 on a signal is enough. For an analog signal, different real values need to be driven. Furthermore, different analog signals might be driven with different values.

2: AMS designs (take ADC as an example) may have different channels, accuracy, and value range, etc.  Developing a configurable verification system to suit different kinds of AMS designs shortens the verification cycle time.

3: Coverage is a metric used to measure the completeness of verifying a design. However, coverage for analog designs cannot be reported easily just like the digital parts. And also, cross coverage between two or more coverage points are important to measure the quality of the verification. 

In current verification flow, some dedicated values are driven on the ADC channel and then the conversion result is checked. There are three disadvantages on this:

1: The ADC with a high accuracy, mountains of dedicated values need to driven on one channel to check the design. Furthermore, driving multiple channels with different values results in exponential growth on the stimulus numbers, even so, some corner values still might be loss.

2: Parametric design is developed to increase the configuration for different chips, but it is not easy to develop the stimulus automatically for the parametric designs. Some manual updates are needed for different designs use different configurations.

3: No coverage reports to ensure the whole range is covered.

WHAT IS THE MOTIVATION?

To overcome these mentioned issues, and to extend the verification environment suit different kinds of AMS designs, one configurable Coverage-Driven Verification (CDV) system based on UVM is developed.

Figure1 configurable CDV system

Figure 1 shows the stricture of the innovation which includes these key components:

Configurable Base_seq: User can extend sequence from the base seq and generate random stimulus with constraint. And also there are two frequent used sequences:

One is about random stimulates flowing standard normal distribution, the other is about random stimulates flowing uniform distribution.

The 2nd key component is Stimulus Generator which can automatic generate stimulus follow a dedicated distribution.

The 3rd is Configurable Monitor: In this monitor, there are two user configurable coverage groups: User can define the coverage group for both the coverage points and cross coverage.

The 4th is Configurable Driver: User can define the channels, accuracy, and value range .etc

The 5th is Configurable Interface: in this interface all the signals are defined as wreal type, which can directly connect to the analog design. and also User can define the channel numbers.

We ca...