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A Nanoscale Standard Cell Look Up Table Characterization Tool Using Robust Semi Empirical Delay Model

IP.com Disclosure Number: IPCOM000234560D
Publication Date: 2014-Jan-17
Document File: 3 page(s) / 213K

Publishing Venue

The IP.com Prior Art Database

Abstract

In static timing analysis (STA), hold and setup time violation checks requires accurate delay measurements of combinational circuits. Look up table (LUT) based methods for delay measurements of these circuits are quite common. These LUTs are pre-characterized for various values of input rise time (TR) and output loads (CL) at various supply voltage and chip temperature nodes. The choice of TR and CL is either completely random or by uniform spacing method. Researchers [1] observed that delay varies linearly with TR up to some break point (TRB). In this paper we analyze the behavior of this break point (TRB) and calculate it for various loads, MOSFET widths, on chip supply voltages and temperature variations and provide a model for (TRB) calculations.

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A Nanoscale Standard Cell Look Up Table Characterization Tool Using Robust Semi Empirical Delay Model

Abstract

In static timing analysis (STA), hold and setup time violation checks requires accurate delay measurements of combinational circuits. Look up table (LUT) based methods for delay measurements of these circuits are quite common. These LUTs are pre-characterized for various values of input rise time (TR) and output loads (CL) at various supply voltage and chip temperature nodes. The choice of TR and CL is either completely random or by uniform spacing method. Researchers [1] observed that delay varies linearly with TR up to some break point (TRB). In this paper we analyze the behavior of this break point (TRB) and calculate it for various loads, MOSFET widths, on chip supply voltages and temperature variations and provide a model for (TRB) calculations.

Methodology

Fast LUT characterization by exploiting linear region in delay versus input rise time curve up to an extent (TRB).  We model the behavior of TRB with various load (CL), VDD and TemperatureOnce we have TRB, we remove the requirements of simulation in the linear region (where TR is less than TRB).

Delay of a CMOS Based NOT Gate with Input Rise Time (TR) for various CL   Showing Linear Regions

TRB variations with CL, VDD and Temperature

Flow chart

Conventional Method                                                 Proposed Method