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Fast test case generation method for the exhaustive layout PCell testing based on the pre-evaluated cell parameters

IP.com Disclosure Number: IPCOM000234561D
Publication Date: 2014-Jan-17
Document File: 5 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Parameterized cells (PCells) are widely used for layout design acceleration and are usually delivered as a part of Process Design Kit (PDK) device libraries. The quality of the PCells affects to the quality and speedup of the layout design. The PCell complexity increases from year to year due to moving to deep nano-meter size and increasing technology restrictions with increasing requirements for PCell testing process. This paper describes new method for optimal test case generation based on pre-evaluated PCell parameter values. The method allows to avoid a lot of extra temporary layout PCell structures in the virtual memory during the test case generation and move from exponential to linear complexity growth from the PCell complexity, allows to reduce requirements for resources and speedup the testing process.

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Fast test case generation method for the exhaustive layout PCell testing

based on the pre-evaluated cell parameters

Abstract

Parameterized cells (PCells) are widely used for layout design acceleration and are usually delivered as a part of Process Design Kit (PDK) device libraries. The quality of the PCells affects to the quality and speedup of the layout design. The PCell complexity increases from year to year due to moving to deep nano-meter size and increasing technology restrictions with increasing requirements for PCell testing process.

This paper describes new method for optimal test case generation based on pre-evaluated PCell parameter values. The method allows to avoid a lot of extra temporary layout PCell structures in the virtual memory during the test case generation and move from exponential to linear complexity growth from the PCell complexity, allows to reduce requirements for resources and speedup the testing process.

Introduction

Deep investigation of the CadenceTM PCells functionality allows to catch non-optimal PCell evaluation: extra temporary layout PCell structures are created in the virtual memory exponentially increasing the memory utilization and time evaluation. The problem is aggravated with number of PCell parameters growing, number of footprint shapes increasing and necessary to test small parameterized layout IP blocks. It makes PCell testing non effective and even impossible in reasonable time based on simplistic method of the straightforward layout PCell test case generation.

To resolve the problem it is proposed new method of the layout test case generation, based on the pre-evaluated PCell parameters. Method allows to exclude a lot of extra temporary layout PCell structures from the virtual memory during the test case generation. It reduces the overall test case generation time and memory usage. The idea is to create each layout PCell instance in the test case in two stages:

  1. calculate all PCell parameter values with callbacks executed before instance layout view creation;
  2. create a PCell instance with these parameter values.

The method allows to sufficiently increase the number of test samples utilizing same compute resources and, as a result, the final quality of the layout PCells testing.

Design and Implementation

Figure 1 demonstrates flowcharts with highlighting the differences (in red rectangles) of the straightforward layout PCell test case generation method versus proposed. The key idea of the proposed method is to add additional symbol and provide all device parameter manipulation for this, non-layout structure which allows to avoid extra temporary layout PCell structures from the virtual memory which are formed when layout PCell parameters are updated. Just one symbol is required per each PCell type independently from number of unique PCell instances. At the end of layout test case generation, this symbol is removed.

Figure 1. Flowchart of a layout test cell generation

 

The Figure 2 has detailed flowch...