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A Method and System for Straining a Highly Scaled Semiconductor Device by Embedding a Stressor Material

IP.com Disclosure Number: IPCOM000234566D
Publication Date: 2014-Jan-17
Document File: 4 page(s) / 100K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and system for straining a negative channel field effect transistor (nFET) region and a SiGe positive channel field effect transistor (pFET) region in a single wafer of scale less than or equal to 14 nanometers, by embedding a SiGe stressor material in the SiGe pFET region.

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A Method and System for Straining a Highly Scaled Semiconductor Device by Embedding a Stressor Material

Disclosed is a method and system for straining a negative channel field effect transistor (nFET) region and a SiGe positive channel field effect transistor (pFET) region in a single wafer of scale less than or equal to 14 nanometers, by embedding a SiGe stressor material in the SiGe pFET region. The single wafer can be used in fabrication of a semiconductor device such as, but not limited to, a fin shaped field effect transistor (FinFET) device and a partially depleted silicon on insulator / extremely thin silicon on insulator (PDSOI /ETSOI) device.

The method and system includes defining a nFET region and a pFET region on the single wafer as shown in fig. 1.

Figure 1

The single wafer can be, but is not limited to, a strained silicon directly on insulator (SSDOI) wafer as illustrated in fig. 2.

1


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Figure 2

The method and system thereafter converts the pFET region into the SiGe pFET region for lessening strain in the pFET region as illustrated in fig . 3. Conversion into the SiGe pFET is accomplished by one or more of, thinning, growing SiGe, diffusion, and condensation.

Figure 3

Fig. 4 depicts gate stack and spacers on the nFET region and the SiGe pFET fabricated by the method and system, subsequent to formation of the SiGe pFET region.

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Figure 4

The method and system thereafter recesses a source , and a drain in the SiGe pFET as show...