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Back End of Line (BEOL) Edge Bead Optimization

IP.com Disclosure Number: IPCOM000234574D
Publication Date: 2014-Jan-20
Document File: 4 page(s) / 583K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to avoid defects that impact chips at the wafer edge and on the wafer caused by the top edge bead region at the wafer edge. The method eliminates the top edge bead removal at Mc/Ca/Via Levels, and adds top edge bead removal to all Aluminum levels that use MUV.

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Back End of Line (

The top edge bead region at the wafer edge has a history of creating defects that impact chips at the wafer edge and randomly on the wafer. The root cause of this problem is that Via/CA levels have a top edge bead cut, whereas Aluminum levels

using MUV resist do not. This leads to all oxide levels being removed in the edge bead region while allowing wires to be poorly printed in the edge region.

Several technologies are affected by this problem:


• P6 M1 TiN filament - lifting M1 lines in edge bead region redeposit on wafer


• 180nm DV flakes - E1 Liner delaminating from edge bead region


• 180nm Brown bond pads - Exposed silicon in dicing channels


• Polyimide hillocks


• 180nm K1 flakes - M1 liner delaminating from edge bead region


• CSOI7RF

Within the process, at Via Levels, approximately 1.5 mm of resist is removed on the top edge of the wafer during the Contact/Via Level photolithography step. The subsequent Reactive Ion Etching (RIE) process removes the dielectric films in this region, which

typically exposes the wafer Silicon. At Aluminum levels, MUV levels do not remove resist on top of the wafer, allowing Aluminum lines to be poorly printed in the edge bead regions.

The current process follows: (Figure 1)

1. Contact/Via level

A. 1.5mm of resist removed on top edge of wafer during Contact/Via level

photo

B. The subsequent RIE process removes the dielectric films in this region, typically exposing wafer silicon. This could lead t...