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An on-chip circuit for generating repair patterns to fit a contiguous virtual address range into a physical memory containing faulty addresses.

IP.com Disclosure Number: IPCOM000234575D
Publication Date: 2014-Jan-20
Document File: 5 page(s) / 290K

Publishing Venue

The IP.com Prior Art Database

Abstract

Previous work (herein referred to as DIS0013) describes a circuit for fitting a contiguous virtual memory space into a physical memory with faults. That circuit relies on a set of Ternary Content Addressable Memory (TCAM) and Static Random Access Memory (SRAM) patterns to perform the actual addressing. A method and on-chip circuit for generating these patterns is desired such that memories may be populated without off-chip assistance.

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Page 01 of 5

An on-

-chip circuit for generating repair patterns to fit a contiguous virtual address

    chip circuit for generating repair patterns to fit a contiguous virtual address range into a physical memory containing faulty addresses .

The invention is a circuit composed of two parts: the range/offset calculator and the pattern generator. The calculator parses the fail data from the memory spaces via the Test Data bus to determine the ranges of good addresses and the required offsets. As

no further processing is required, the offsets are written directly to the SRAM in the DIS0013 circuit. The ranges must be encoded into TCAM format and are passed to the generator for this purpose. The generator produces TCAM patterns that are written into the TCAM in the DIS0013 circuit. A circuit diagram of the invention is shown in Figure


1.

Figure 1: Block diagram of circuit

The DIS0013 circuit requires that the TCAM calculate a strictly-less-than function for each range. This requires a set of TCAM entries for each range that cover the range

with binary blocks. For example, less-than-25 requires TCAM entries 0**** (0-15), 10*** (16-23), and 11000 (24). The pattern generator produces these patterns. Figure 2 gives the detailed circuit implementation of the pattern generator.

Figure 2: Circuit diagram of the pattern generator

1


Page 02 of 5

The valid signal is generated from each address bit in turn via a shift register; a valid pattern is produced from each one in the address. The address is also held in a register ahead of the encoders; this protects the circuit from changes to the address input and is not necessary if the stability of the input address is guaranteed. The encoders translate from the 0 or 1 bits of the address to the ternary digits (trits) '0' and '1' of the TCAM encoding. The muxes create the bitline patterns, keeping the more-significant trits the same, setting the middle trit to '0', and setting the less- significant trits to ALWAYS-MATCH. The location of the middle trit is shifted right-to-left by the left-shift-by-two register. The drawing shows just two muxes and encoders, but in fact there are N of each, and the widt...