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Method and System for Forecasting Estimation Risk of Chip Size Based on Maturity of Design Data

IP.com Disclosure Number: IPCOM000234592D
Publication Date: 2014-Jan-21
Document File: 3 page(s) / 242K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for forecasting estimation risk of chip size based on maturity of design data is disclosed.

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Method and System for Forecasting Estimation Risk of Chip Size Based on Maturity of Design Data

Disclosed is a method and system for forecasting estimation risk of chip size based on maturity of design data. In general, different Intellectual property (IP) modules from different sources are used in developing a chip. However, it becomes necessary to forecast estimation risk of chip size based on sources of IP used.

Initially, different risk factors are assigned at areas of each type of Intellectual Property (IP) used in the chip. As shown in fig. 1, the risk factors are assigned based on quantity and quality of data used in estimation of IP.

Figure 1

For example, as shown in fig. 1, undeveloped IP which comprises 12% of the chip size and has a very high risk of inaccuracy is assigned a risk factor of 100. Similarly, a company developed IP, which comprises 8% of the chip size, is assigned a risk factor of 50. Additionally, a risk factor of 0 is assigned to released and qualified IP which has low risk of inaccuracy.

Thereafter, different risk factors are assigned to IP Overhead based on maturity of design methodology. The IP overhead may include clock trees, test overhead, decap cells, fuses, power optimization logic and timing closure logic among other. As shown

in fig. 2, clocking comprises 2% of chip size whereas Built-in Self Test (BIST) logic comprises 6 % of chip size. Similarly, decap cells comprises 4% of chip size whereas timing closure comprises 2% of ch...