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Method and System for Reducing Voltage Ripple and Noise using On-Chip Switched-Capacitor DC-DC Converter with Pulse Capacitance Modulation

IP.com Disclosure Number: IPCOM000234651D
Publication Date: 2014-Jan-24
Document File: 5 page(s) / 200K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for reducing voltage ripple and noise using on-chip switched-capacitor DC-DC converter with pulse capacitance modulation.

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Method and System for Reducing Voltage Ripple and Noise using On - Switched- -Capacitor DC

Capacitor DC -

-DC Converter with Pulse Capacitance Modulation

DC Converter with Pulse Capacitance Modulation

On-chip power delivery is important for high performance processors , where power

consumption is high and power losses due to package parasitics are not negligible . With step-down on-chip voltage converters, board-level DC-DC converters can improve efficiency and reduced current on board leads to reduce power loss . The power loss is generally due to resistive drops (IR) and inductive supply noise margins (Ldi/dt). Switched-capacitor (SC) circuits inherently enable very high efficiency for ratioed conversion which can enable high voltage power delivery to the chip. In voltage regulation using switched-capacitor converters, there is an inherent output voltage ripple induced by the two phases of operation. Without proper management, output voltage ripple can be very high, resulting in large voltage overhead margins, which

degrade system-level power. In SC voltage regulators, ripple reduction is adjusted externally. The number of interleaved SC phases can be controlled for ripple mitigation, but the outcome is bounded by the inherent single -phase ripple.

Disclosed is a method and system for reducing voltage ripple and noise using on -chip switched-capacitor DC-DC converter with pulse capacitance modulation. Fig. 1 illustrates the method and system which provides new circuit techniques that reduce the ripple by intra-phase capacitance and delay modulation with closed -loop regulation control. The method and system reduces output ripple and transient noise using pulse capacitance modulation (PCM), intra-phase delay modulation (IPDM) and flying capacitance floating technique.

Figure 1

Firstly, PCM modulates the flying capacitance of a Switched -Capacitor (SC) to the optimal value for minimum output ripple. The desired value is calculated in run-time based on history of past regulation cycles that reflect load current . The PCM calculates desired flying capacitance (Cfly). Based on the calculated Cfly, the PCM modulates Cfly and runs SC all the time. In this way, the flying capacitance is adjusted to be only as large

1

-Chip

Chip


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as needed to deliver the load current, which minimizes ripple at the output.

Secondly, IPDM is used for further ripple reduction through multi -phase interleaving,

which enables intra-phase interleaving with finer time resoluti...