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Method of enhanced channel strain using suspended source/drain FinFETs

IP.com Disclosure Number: IPCOM000234689D
Publication Date: 2014-Jan-28
Document File: 3 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a method to use additive strain induction for strained fin Field Effect Transistors (finFETs) as a means of boosting the strain in the channel.

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Method of enhanced channel strain using suspended source /

Application of high levels of strain to three-dimensional (3D) structures such as fin Field Effect Transistors (finFETs) is challenging. Common methods such as embedded source/drain (S/D) usually fail, especially at tighter contacted gate pitches.

Substrate strain engineering may be a practical approach; however, the amount of strain may not be sufficient due to several factors such as restrictions for the epitaxial critical thickness. As a result, a method is needed to further boost the strain in the channel.

The novel approach is to use additive strain induction in the channel of strained finFETs

(i.e. compressively strained-Silicon Germanium (SiGe), III-V on bulk, or insulator using suspended source and drain). A small amount of suspension in the S /D regions can relax the strain in the S/D and transfer the force due to volume expansion of the already compressed material to the channel. The approach removes the dummy gate to increase the strain and fill in a new dummy gate to "freeze" the strain . This results in increased uniaxial strain in the channel of the FinFET .

Figure 1: Fin, Gate, Spacer, and Dummy Oxide Stressor Formation

• Fin material can be either compressively strained-SiGe, Ge or III-V

• Material B can be any insulator (e.g., SiO2, HfO2, InAlAs, etc.) or a semiconductor for the case of bulk finFET

Figure 2: S/D Suspension, Dummy Spacer Removal

/drain FinFETs

drain FinFETs


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