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Method of Formation of Folded Channel Transistor

IP.com Disclosure Number: IPCOM000234693D
Publication Date: 2014-Jan-28
Document File: 5 page(s) / 114K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to reduce Short-Channel Effects (SCEs) by relaxing the effective channel length scaling while aggressively scaling the contact pitch using a folded channel architecture.

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Method of Formation of Folded Channel Transistor

As gate pitch size is aggressively scaled, Short-Channel Effects (SCEs) become a serious problem, even for fin Field Effect Transistors (finFETs) or Extremely Thin Semiconductor on Insulator (ET-SOI)-like structures. For example, for a contact size of 10nm, total spacer thickness of 2x5nm=10nm and 33nm C-Preprocessor (CPP), the room for gate material in a Replacement Metal Gate (RMG) approach is only 13nm. At

the same time, counting for total 4nm High-K (HK) material, only 9nm of room remains for MG, where SCE and direct Source/Drain (S/D) tunneling can be the real issue.

The novel solution is to relax the effective channel length scaling while aggressively scaling the contact pitch using a folded channel architecture . This also allows the presence of multiple effective gate lengths (L) and, thus, multiple threshold voltages at a given pitch size, while controlling short channel effects.

Figure 1: Starting Substrates

Figure 2: Dummy Gate Pattern

Figure 3: Spacer Formation

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Figure 4: Recess Crystalline Oxide under the Spacer

Figure 5: Heavily Doped S/D Epitaxy

Figure 6: Silicidation, Inter-Layer Dialectric (ILD) formation and Chemical-Mechanical Planarization (CMP)

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Figure 7: Dummy Gate Removal

Figure 8: Crystalline Oxide Recess

Figure 9: Channel Epitaxy

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Channel can be Germanium (Ge), strained-Ge, III-V, Germanium Tin (GeSn), strained-Silicon (Si)

Figure 10: HK Deposition...