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Browse Prior Art Database

Methodology to Restrict Operational Environmental Conditions of System on a Chip

IP.com Disclosure Number: IPCOM000234772D
Publication Date: 2014-Feb-03
Document File: 2 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a methodology to restrict operational environmental conditions of System on a Chip (SoC).

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 2

Methodology to Restrict Operational Environmental Conditions of System on a Chip

Hacking of mass market devices has become a worldwide phenomena. Everyone one from the teenager still living at home to the university PhD student and even university professors have entered into this arena in the name of research, consumer advocacy, and stealing IP. Because of the wide range of skills and tools which support these hackers, it has become increasingly difficult to protect design IP without impacting your customer's experience. Hackers use the fact that chips are designed to function over a wide range of environmental conditions to impact how the circuits function. These differing conditions cause certain circuits to behave predictably but in a much different way than designed. These functional holes are then used to get around security functions inside the chip. A way of determining that the chip is in an extreme environmental condition and preventing boot-up is required.

    This disclosure will teach how to use specially designed performance sort ring oscillators (PSROs) to determine if a chip is in an approved environmental condition and prevent boot-up if it is not. This will be accomplished by designing several PSROs to be sensitive to temperate, voltage, and system frequency. Each PSRO will have an acceptable range of running frequencies with respect to temperature, voltage, or system frequency frequency. These will create a envelope in which the chip will be allowed to function. Inside the eFuse macro or other nonvolatile memory, the time the PSROs can be sampled as well as the high- and low-frequency ranges can be stored to cover for chip-to-chip variation.

    Each PSRO will be designed to fail at a certain point of temperature, voltage, and system frequency. These PSROs will be characterized at chip test and eFuses wi...