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Micro-adaptive Test Algorithm for Magnetic Memory Cell Development

IP.com Disclosure Number: IPCOM000234805D
Publication Date: 2014-Feb-07
Document File: 5 page(s) / 94K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a testing infrastructure for Magnetic Memory Cell Development that incorporates a test flow algorithm, a test environment, and two self-modifying test code algorithms. This approach automatically micro-adapts test code on a die-by-die basis, adapting analog biases and test patterns to the parametric parameters of the cells in the memory as well as the bit map of yielding cells.

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Micro-

-adaptive Test Algorithm for Magnetic Memory Cell Development

adaptive Test Algorithm for Magnetic Memory Cell Development

Magnetoresistive Random Access Memory (MRAM) technology has a number of attractive attributes, including Static Random Access Memory (SRAM)-like access times, non-volatility, and demonstrated superior endurance to flash and Phase -Change Memory (PCM) technologies. Moreover, as Complementary Metal-Oxide Semiconductor (CMOS) scaling passes the 20 nm node, the requirement to maintain a minimum cell capacitance and selection transistor off leakage below 1 fA make scaling of the conventional Dynamic Random Access Memory (DRAM) cell increasingly more difficult.

MRAM cells based on the one magnetic tunnel junction (MTJ) one transistor (1TJ cell) utilizing spin torque switching are particularly attractive because of a demonstrated potential to scale at least down to a 25nm cell (M. Gajek, 2012). The most technologically important configuration of the MTJ utilizes a magnetic stack system in

which the magnetization of the magnetic layers points in a direction perpendicular to the

junction substrate (Post Metallization Anneal (PMA) stacks).

The development of the magnetic memory cell poses a number of challenges in the areas of magnetic materials, chip fabrication process, array design, and test. The MRAM cell consists of several magnetic layers including a free layer with a selectable magnetic state, and a fixed magnetization layer. In the process of developing a viable MRAM technology, and ultimately in manufacturing the MRAM, test of the memory and acquisition of process control data is critical. Careful monitoring and measurement of the magnetic properties of both the free layer and pinned layer are required .

Unfortunately, during the developmental phase of a new memory cell design , yield of each unit process step is often quite low. For example, development of a new material system often requires re-engineering a tunnel barrier. Initial stacks often contain many shorted or open circuit devices that are untestable. In addition, unit process integration modules often require significant iteration and adjustment before device yield improves .

In addition, the material development studies often entail testing parameter "wedges" in

which the material properties of the magnetic cells are intentionally varied across a

wafer, yielding devices with widely varying parametric properties from die to die. Working with these device variations makes it difficult to evaluate a given process .

A design is needed for a testing infrastructure that automatically micro -adapts test code on a die-by-die basis, adapting analog biases and test patterns to the parametric parameters of the cells in the memory as well as the bit map of yielding cells . This kind of test flow is radically different from the more traditional test approach , which runs a

fixed suite of software against each die, with a set of fixed bias levels and test...