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Method and System for Developing a Magneto Resistive Random Access Memory (MRAM) IC Tester

IP.com Disclosure Number: IPCOM000234810D
Publication Date: 2014-Feb-07
Document File: 5 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for developing a Magneto Resistive Random Access Memory (MRAM) IC Tester.

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This is the abbreviated version, containing approximately 23% of the total text.

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Method and System for Developing a Magneto Resistive Random Access Memory (

(MRAM

MRAM) )

IC Tester

IC Tester

Disclosed is a method and system for developing non volatile magneto resistive random access memory (MRAM) IC tester. The method and system provides a tester that is capable of testing magnetic memory and acquiring critical process control data that are required for magnetic cell characterization. The tester carefully monitors and measures magnetic layer properties such as, but are not limited to, free layer and pinned layer.

Figure 1 illustrates an MRAM test system incorporated with an IC tester that operates in logic mode, along with a high speed parametric measurement unit (PMU) and a magnetic controller. The IC tester generates test patterns in memory test mode ,

whereas PMU unit and magnetic controller generate test patterns in logic mode .

Figure 1

An electromagnet is coupled and mounted close to a device under test (DUT) at the vicinity of probe station. The magnet applies required magnetic fields to the DUT to enable various magnetic tests to be performed. The PMU, shown in the figure 1, which

is external to the IC tester, provides parametric measurement capabilities for performing electrical resistance checks and other types of electrical characterization on the MRAM .

A major component of the MRAM test system is a highly flexible , bidirectional trigger bus, which links the digital tester to the magnet controller and the high speed PMU . The trigger bus allows either parametric or digital measurements of the MRAM to be precisely synchronized with the digital signals applied by the digital tester. Thus, a number of purely functional, as well as parametric tests (both electrical and magnetic) can be performed in a highly efficient "digital mode" by using the trigger bus architecture on the MRAM. The one or more parametric/magnetic tests include such as, but not limited to, magnetic functional test, electrical parametric test, and magnetic parametric test.

Functional test of the MRAM is performed by the IC tester using conventional

1


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techniques. However, an unconventional requirement of MRAM process control is valuation of magnetic offset of the fixed magnetic layer . This offset can arise from many causes, and deteriorates the operating margins of the MRAM . For this reason it needs to be evaluated, and this evaluation is accomplished by combining digital functional tests with application of a range of externally applied offset fields , using the electromagnet. Additionally, the electromagnet has another application in functional test. An externally applied field can be used to blanket write the MRAM to either
"0" (parallel P) or "1" (anti parallel AP) state. Thus, magnetic blanket writing is used in extremely efficient blanket write/read test, to check out the functionality of each cell. This kind of test capability is particularly important when performing failure analysis of stuck faults. For exampl...