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Dual Die Design for SOIC EP Package

IP.com Disclosure Number: IPCOM000234834D
Publication Date: 2014-Feb-10
Document File: 2 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

Current SOIC dual die package sometimes experience die crack issues. We propose a new dual die SOIC exposed pad (EP) package design that addresses this die crack issue. The proposed design aims to reduce die pad stress and eliminate die crack defects. The proposed design combines EP with non-EP to address the aforementioned issue.

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Dual Die Design for SOIC EP Package

Abstract

Current SOIC dual die package sometimes experience die crack issues.  We propose a new dual die SOIC exposed pad (EP) package design that addresses this die crack issue.  The proposed design aims to reduce die pad stress and eliminate die crack defects.  The proposed design combines EP with non-EP to address the aforementioned issue.

Introduction

In a package having a power die and a control die, the two dies are attached to the same lead frame.  Post assembly interaction stress was experienced that caused die cracking.  We propose a new package design in which the power die and the control die are not on a single planar surface in order to relieve interaction stress and overcome the die cracking issue.  The proposed design combines an exposed pad and non-exposed pad and placing the die that needs high heat conducting on the exposed pad.

Design and Implementation

Figure 1 shows a current dual die package design, where the power die and the control die are on a planar surface.

Figure 1.  current dual die package design

 
                                   

Figure 2 shows our proposed package design, which is a combination non-exposed pad and exposed pad and the power and control dies are not on a planar surface.

Figure 2.  Proposed dual die package design

 

 Figure 3 shows the cross-sectional and top views of the proposed design

Figure 3.  Cross-section and top view of proposed design

 

The pr...