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A Resource Shared Integer Divider and Square Root Arithmetic Unit

IP.com Disclosure Number: IPCOM000234938D
Publication Date: 2014-Feb-17
Document File: 5 page(s) / 325K

Publishing Venue

The IP.com Prior Art Database

Abstract

Most low cost MCUs (include ARM Cortex M0/M0+ core built with ARMv6-M ISA) do not have a hardware Integer Divider, nor the unsigned square root function, but some applications (such as PMSM motor control) need these functions. Such operations are implemented in a software function library and consume several hundreds or even thousands of CPU cycles to calculate one 32bit divider and/or square root calculation. In this paper we introduce a resource shared integer divider and square root arithmetic unit that has a low gate count. The supported integer divide operations include 32/32 signed and unsigned calculations.

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A Resource Shared Integer Divider and Square Root Arithmetic Unit

Abstract

Most low cost MCUs (include ARM Cortex M0/M0+ core built with ARMv6-M ISA) do not have a hardware Integer Divider, nor the unsigned square root function, but some applications (such as PMSM motor control) need these functions.  Such operations are implemented in a software function library and consume several hundreds or even thousands of CPU cycles to calculate one 32bit divider and/or square root calculation.  In this paper we introduce a resource shared integer divider and square root arithmetic unit that has a low gate count.  The supported integer divide operations include 32/32 signed and unsigned calculations.

Introduction

Figure 1 shows the over-all structure of the proposed arithmetic engine.  The division engine is built with the “Shift, Test and Restore” algorithm, which is the most low cost integer divider and is actually the same as the simple "pencil and paper" algorithm.  It starts from the dividend highest bit, and subtracted by divisor to test if it is larger than the divisor.  If it is larger, then the quotient bit will be ‘1’; otherwise it is ‘0’, and the dividend needs to be restored.  This is called test and restore.  After it is done, both dividend and quotient will left shift and do the test and restore for the next bit.

 

When manually calculating the unsigned integer square root, the calculation process is very similar to the dividing process.  Beginning with the left-most pair of digits, we perform the following procedure for each pair:

1.                   Starting on the left, bring down the most significant (leftmost) pair of digits not yet used (if all the digits have been used, write "00") and write them to the right of the remainder from the previous step (on the first step, there will be no remainder).

2.                   Find root, and remainder as follows:

      1. Trial with root[1:0] = 2’b01 and subtract it from radicand[31:30];
      2. If the result in i is minus, root[1:0] = 2’b00, partial remainder should be radicand[31:30] otherwise root[1:0] = 2’b01 and partial remainder should be radicand[31:30] – 2’b01;
      3. Left shift root by 2, left shift radicand by 2, left shift partial remainder by 2 and fill its right most two bits with radicand[31:30]

3.                   Repeat 2 until the calculation is complete (determined by the actual valid radicand width).

From the above steps we find the shift circuit and the subtractor can be completely reused by both division and square root calculation.

 
 

Figure1. Block diagram

 
 

Design and Implementation

In implementation, there...