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PMIC (Power Management Integrated Circuit) Authentication for System Security

IP.com Disclosure Number: IPCOM000234939D
Publication Date: 2014-Feb-17
Document File: 5 page(s) / 399K

Publishing Venue

The IP.com Prior Art Database

Abstract

An authentication method is disclosed that uses the Power Management Integrated Circuit (PMIC) registers and logic to perform encryption design, collaborating with processor to implement system security, control the system power start-up mechanism, and protect the security of the system and product. The proposed encryption technique saves the cost of external hardware and does not require an external power supply.

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PMIC (Power Management Integrated Circuit) Authentication for System Security

ABSTRACT

An authentication method is disclosed that uses the Power Management Integrated Circuit (PMIC) registers and logic to perform encryption design, collaborating with processor to implement system security, control the system power start-up mechanism, and protect the security of the system and product.  The proposed encryption technique saves the cost of external hardware and does not require an external power supply.

PMIC AUTHENTICATION STEPS

  1. PMIC internally provide Read/Write registers and OTP (One Time Programmable) registers.
  2. PMIC’s all registers will communicate with processor through a communication bus which will be powered by PMIC itself.
  3. Every PMIC will provide a unique encryption key or algorithm F() by chip vendor, and PMIC will provide OTP registers with burned code Xs and code Ys, and Ys=F(Xs).
  4. The processor will firstly perform initial password authentication. Only with this successful password authenticating, the processor can continuously access to read and write the Read/Write registers and read OTP registers from PMIC.
  5. After the initial password authenticated, the processor then read Xs and Ys.
  6. The processor adopts encryption algorithm F() provided by chip vendor, and calculate Ym=F(Xs).
  7. Afterwards, the processor compares the Ym and Ys, if they’re same, notify the PMIC to enable other output rails to power on the whole system legally; if not, it’s illegal, then inform the PMIC to power off all the outputs, hence the whole system never powers on.
  8. Meanwhile authentication cycle times can be configured by the processor. If the authentication fails and the limit times are exceeded, then system will end up in powering off status.  


DRAWINGS

 


FIG. 1 PMIC Authentication Hardware Block Diagram

 FIG. 2 PMIC Authentication flow chart

FIG. 1 is a block diagram illustrating a PMIC authentication system.  The authentication system includes a PMIC 110, a processor 140, a memory 150, and some peripherals 160.  The vendor of the PMIC 110 will provide a unique initial password and a unique encryption key F(). which is an algorithm. 

The PMIC 110 includes: R/W Registers 112. which is the read and write registers, logic control unit 130, OTP (One Time Programmable) registers 114, which is a nonvolatile memory, and other blocks 125.  The OTP registers 114 were previously burned with Xs 115, which is the confidential source code, Ys 117, which is the generated code encrypted from the Xs 115 by the encryption key F(), an initial password 127, and a start-up sequence 119.  Where Ys=F(Xs).   

A communication bus 132 connects the PMIC 110 and the processor 140 and the processor 140 can communicate with the memory 150 and peripherals 160 through a bus 151 and a bus 161.  The PMIC 110 will provide V0 output rail, which is constantly on to the processor 140 to provide pull up power to the communication bus 132.  As the input power is applied to the...