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Latch Based Architecture for Data retention and SRPG testing of Sequential Cells on Silicon

IP.com Disclosure Number: IPCOM000234980D
Publication Date: 2014-Feb-20
Document File: 3 page(s) / 264K

Publishing Venue

The IP.com Prior Art Database

Abstract

Tester time reduction for post silicon validation has always been the area of concern. Data retention and SRPG testing of standard cells requires huge amount of tester time because of the voltage stress(~ 0.5 sec/Std. cell) involved in these techniques. This paper presents an architecture for Std. cells validation wherein no. of voltage stress events is minimized without affecting the coverage. An architecture involving latch based input interface is presented to achieve minimum no. of stress events to reduce tester time manifold times.

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Latch Based Architecture for Data retention and SRPG testing of Sequential Cells on Silicon

 

Abstract—Tester time reduction for post silicon validation has always been  the area of concern. Data retention and SRPG testing of standard cells requires huge amount of tester time because of the voltage stress(~ 0.5 sec/Std. cell) involved in these techniques. This paper presents an architecture for Std. cells validation wherein no. of voltage stress events is minimized without affecting the coverage. An architecture involving latch based input interface is presented to achieve minimum no. of stress events to reduce tester time manifold times.

Keywords— Std. Cells Validation, Test Time reduction

I.  Introduction

For a standard cell designer, meeting design constraints is as important as getting it qualified it’s usage on  SOC. Standard cell designs need to be functionally as well as qualitatively validated on silicon before employing them on SOC for any technology node. Standard cells validation include checks like “Data Retention testing” and “SRPG testing” apart from functionality checks. To serve all this, “All Cells” architecture   in Figure 1 is used on test vehicles wherein input vectors are applied to check the expected behavior at output.

A full blown Std. Cell library consists of thousands of cells which need to go through these testings. Owing to the large number of elements to be tested ,“tester time” reduction has always been a top requirement.

The paper is organized as follows: In section II, we describe the scope of optimization for tester time on test-bench and architectural level. In section III, we described functional, Data Retention and SRPG testing for Std. cells. In section IV, All Cells architecture conventionally used on test vehicles to validate Std. cells is described. In section V, we presented proposed architecture which reduces tester time manifold times for Data retention and SRPG testing of Std. cells. In section VI, we described Data Retention Testing process through a flowchart for conventional and proposed architecture. In section VII, we have presented the proof of concept for the proposed art .In section VIII, we concluded with the application of proposed art.

II.  Optimization

There can be architectural level as well as testbench level of optimizations which can help reduce overall “tester time”. These optimizations can be meant to any of the three categories i.e Functional testing, Data Retention testing, SRPG testing.

Architectural level optimizations can be modification in All Cells architecture of Figure 1 which facilitates parallel testing thereby reducing “tester time”. Testbench level optimizations can include smart sequencing of test vectors, to avoid repetition of test vectors.

III.  Functional, Data Retention, Srpg Testing 

In functional testing, a set of input vectors is applied to observe the expected output. In Data Retention testing ,an input is applied and outpu...