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Method for Allowing Large Block Synthesis (LBS) Designs to be Checked for Design for Test (DFT) Compliance

IP.com Disclosure Number: IPCOM000234985D
Publication Date: 2014-Feb-21
Document File: 1 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for allowing Large Block Synthesis (LBS) designs to be checked for Design for Test (DFT) compliance before embedding Intellectual Property (IP) designs.

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Method for Allowing Large Block Synthesis (LBS) Designs to be Checked for Design for Test (DFT) Compliance

Typically companies are using more and more Large Block Synthesis (LBS) blocks. LBS blocks may include one or more embedded Intellectual Property (IP) designs. The embedded IP designs are sometimes completed after the LBS block, which delays the

Design for Test (DFT) work on the LBS block. In addition, embedded IP designs which are tested by Array Built in Self Test (ABIST) may cloud the test coverage estimates at the LBS level, and may cause run times for LBS blocks to explode from less than a day to 4 or more days, which also delays LBS designs.

Disclosed is a method for allowing Large Block Synthesis (LBS) designs to be checked for Design for Test (DFT) compliance before embedding Intellectual Property (IP) designs.

In accordance with the method, DFT Analysis (DFTA) is performed to verify that designs are DFT compliant. Embedded IP in LBS blocks are flagged as not complete or as tested by ABIST. When a designer runs a LBS block using DFTA, DFTA creates a boundary model for flagged embedded IP designs. Boundary models for flagged embedded IP designs are created and are called white box models as illustrated in the Figure. Two types of embedded IP, IP def and IP gxi are illustrated in the Figure.

Figure

The white box model for an embedded IP design includes latches that receive data from embedded IP input pins, and latches that drive data to embedded IP ou...