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Method and System for Controlling a Vernier Structure of a Backside Grinding of Through Silicon Vias Wafers

IP.com Disclosure Number: IPCOM000235018D
Publication Date: 2014-Feb-24
Document File: 3 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for controlling a vernier structure of a backside grinding of Through Silicon Vias (TSV) wafers.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 88% of the total text.

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Method and System for Controlling a Vernier Structure of a Backside Grinding of Through Silicon Vias Wafers

Disclosed is a method and system for controlling a vernier structure of a backside grinding of Through Silicon Vias (TSV) wafers.

The method and system provides the vernier test structure to monitor the grinding of a TSV wafer and determine if the grinding is either insufficient or excessive. The vernier test structure utilizes a series of TSVs of different lengths, which results in different

trench depths due to Reactive Ion Etching (RIE) lag. The test structure has TSV lengths or depths that are both above and below a desired TSV length or depth such that both insufficient grind and excessive grind can be monitored.

Fig. 1 illustrates top view of the vernier test structure for monitoring the grinding.

Figure 1

As shown in Fig. 1 the length of TSV1 is 80µm, length of TSV2 is 50 µm and length of TSV3 is 20 µm.

Fig. 2 illustrates a cross-section view of the vernier test structure.

Figure 2

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Fig. 3 illustrates a top view of front side of a wafer that shows layout of the vernier test structure across the wafer.

Figure 3

Fig. 4(a), Fig. 4(b) and Fig. 4(c) illustrate backside of the wafer after the grinding or after both grinding and polishing.

Figure 4(a)

Fig. 4(a) represents the vernier test structure when the grinding is insufficient.

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Figure 4(a)

Fig. 4(b) represents the vernier test structure when the grinding is sufficient.

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