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Structure for adjusting drive current in silicon nanowire devices

IP.com Disclosure Number: IPCOM000235019D
Publication Date: 2014-Feb-24
Document File: 3 page(s) / 53K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure that enables Static Random Access Memory (SRAM) gamma ratio adjustment in silicon nanowire (NW) technology with stacked wires in some locations and single wire in others, in particular, SRAM positive channel Field Effect Transistors (pFET).

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Structure for adjusting drive current in silicon nanowire devices

Fin Field Effect Transistors (FinFETs) and, by extension, nanowire (NW), Static Random Access Memory (SRAM) cells prefer narrower positive channel FET (pFET) devices for optimum stability.

For increased current per footprint, it may be desirable to stack two (or more) silicon nanowires in the same gate. For certain purposes, notably pFETs in 6T SRAMs, the additional current may not be desired for optimum stability.

The novel structure enables SRAM gamma ratio adjustment in silicon NW technology

with stacked wires in some locations and single wire in others, in particular, SRAM

pFET.

Figure 1: Single NW transistor (Contact to gate schematically illustrated over gate) (included for completeness)

Figure 2: Stacked NW transistor (Contact to gate schematically illustrated over gate) in

which both wires are equally conductive. Provides more drive current per area for most devices.

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Implanting dopants at low energy can electrically disable the upper wire (or wires) from providing current in selected devices. This may be advantageous where the extra current is not desired.

One such example is a pfet in a 6T SRAM

Figure 3: Stacked NW transistor in which the top device has been effectively disabled by heavy doping in the wire. Doping is selective by mask, and into the top wire only by very low energy.

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