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Method for Encapsulating a Copper Plug Structure with a Sidewall Spacer and a Cobalt-Tungsten Cap Layer

IP.com Disclosure Number: IPCOM000235021D
Publication Date: 2014-Feb-24
Document File: 4 page(s) / 119K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for providing a novel "plug-first" process to form a structure that is encapsulated with a sidewall spacer and an inert low temperature Cobalt-Tungsten (Co-W) cap layer on a chip-level copper final via plug. The method immunes the attack to the plug structure from process chemicals.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

Method for Encapsulating a Copper Plug Structure with a Sidewall Spacer and a Cobalt-

-Tungsten Cap Layer

Tungsten Cap Layer

Traditionally, an aluminum plug structure has been employed as a package interconnect on a standard SCM, MCM, 2D, 2.5D or 3D part. However, a chip-level copper final via plug provides a structure that has both a lower build cost and better current-carrying (and electromigration) capability than aluminum. The present methodology for producing the plug structure has several issues that makes the methodology less than optimal. Firstly, the method involves the use of an abrasive Chemical-Mechanical Polish (CMP) process on a surface of the polyimide in order to planarize the copper plug, leaving the plug flush (planar) with the polyimide that

surrounds the plug.

Fig. 1 illustrates a standard chip-level copper final via plug with the application of CMP process.

Fig. 1

As illustrated in Fig. 1, the CMP process initiates scratching and significant roughening of the surface. Thus, the process typically leaves point defects or small puddles of residual metal. In addition, the process creates a chip-edge crackstop structure that does not conform to the traditional requirements for crackstop integrity. The crackstop can be formed so as to leave copper exposed on the finished wafer/chip part, that can then corrode or give rise to other reliability risk. Alternately, the crackstop can be covered with a continuous film of dielectric material that extends from the diced chip edge across the crackstop and into the active chip area, thus serving as a potential medium for crack propagation. Another disadvantage of this approach is associated with the formation of a topographical "edge" on the plug via as the result of standard surface cleanup processing with O2 ash after plug formation.

The method disclosed herein provides a "plug-first" process to form a structure that is encapsulated with a sidewall spacer and an inert low temperature Cobalt-Tungsten (Co-W) cap layer on a chip-level copper final via plug. The method immunes the attack to the plug structure from process chemicals. This copper final via plug structure is typically used with a C4 Pb Free solder bump or Cu Pillar Interconnect (CPI).

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Page 02 of 4

The method begins with an exemplary structure of the unique chip-level copper final via plug with an inert low temperature Cobalt-Tungsten (Co-W) cap layer as illust...