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Method for flash memory data access

IP.com Disclosure Number: IPCOM000235422D
Publication Date: 2014-Feb-26
Document File: 3 page(s) / 52K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method in the area of supply voltage management of flash based systems for effective control of droop events to improve reliability and performance

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Method for flash memory data access

In flash-based designs where an array of flash devices are employed when a data access request comes in, for performance reasons, data has to be accessed in parallel from many devices simultaneously. In this scenario, the entire flash array is suddenly turned on, and this causes a huge di/dt. Regulator design points typically account for moderate droop events. Repetitive surge events close to supply tolerance levels would stress the device heavily and, therefore, early mode issues and/or degradation leading to higher failure rate. The idea disclosed here:

This method proposes to have "queue monitor logic (QM)" that can reside in flash controller or flash device and "voltage controller logic (VC)" that can reside in flash controller or flash device or system backplane.

It further proposes that QM logic monitors the read/write/erase queue and, if it's empty, it can

send a command/signal to the VC logic which interacts with the voltage regulator module (VRM) to change the voltage levels.

Based on monitoring the queue by QM logic, when a write operation comes in, voltage level

can be bumped up and, therefore, during a huge di/dt event, required voltage level can be maintained to counteract the droop event.

VC logic can also monitor the voltage levels. If the voltage level has reached a certain low

threshold, for any writes that comes in thereafter, it can increase the voltage level, so that the "supercap" is not triggered (and per...