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Multidimensional addressing memory management unit and accelerator

IP.com Disclosure Number: IPCOM000235481D
Publication Date: 2014-Mar-04
Document File: 2 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a system that generates hardware to improve memory performance of those software applications using multidimensional arrays.

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Multidimensional addressing memory management unit and accelerator

Multidimensional arrays, for example 2dim, 3dim, are commonly used in scientific and commercial applications. The Morton addressing, also known as the Z-order and space filling curve, is used in mapping 2dim and 3dim arrays to 1dim memory while exploiting spatial locality in multidimensions. By rearranging address bits, the array elements are placed in a one-dimensional memory such that the array elements nearby in the multidimensional array are also placed nearby in the underlying 1-dim memory. Exploiting the spatial locality improves memory performance by reducing both cache misses and memory bandwidth utilization.

The novel contribution is a hardware system to improve memory performance of those software applications using multidimensional arrays. The is an address permutation network in the load/store interface in of a system bus attached accelerator , for example PCIe. The accelerator interface comprises an address line permutation network , an address decoder, and associated control logic. The accelerator programmer chooses pages for which the addresses are to be permuted and indicates whether 2d or 3d addressing modes should be used. The address decoder instructs the permutation network to shuffle address bits accordingly.

Figure 1: Main idea: interleave the address bits

Figure 2: Simple use case

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