Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Time division multiplex logic sharing in synthesis

IP.com Disclosure Number: IPCOM000235560D
Publication Date: 2014-Mar-10
Document File: 7 page(s) / 253K

Publishing Venue

The IP.com Prior Art Database

Abstract

In this disclosure, an automatic method embedded in synthesis flow via time division multiplex logic sharing is proposed in this disclosure to fully leverage frequency capability of particular technology node without any code re-development work. This method includes an automatic logic sharing flow via TDM structure building, a logic cloud sharing engine for logic sharing pool generation, a judgment Engine for generation of optimal/qualified sharing logic cloud, and TDM structure builder together with its constraints generator with considering clock/ASST insertion for the generation of logic sharing netlist and physical design constraints. This method can minimize the leakage power with the die economic consumption on the remapping design.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 43% of the total text.

Page 01 of 7

Time division multiplex logic sharing in synthesis


Along with the advanced semiconductor process technologies development, several circuits could run at the high clock frequency, which were targeted at lower frequency in the original technology node.


For each technology node, IP core (like SRAM/RF/RA), as well as stand cell librarty, are designed for particular frequency capability based on power-performance trade-off.


Leakage power has become a top concern for integrated circuits design in deep submicron process technology. It has increased 30%-50% under 65nm node and even trend to dominate the power consumption. Then keeping die size smaller as much as possible is very important for leakage power dominated chip.


Therefore, based on the points listed above, to fully leverage frequency capability and minimize the leakage power is one key consideration for a chip to be successful.


For the remap design from one technology node to another, if you want to fully utilize the frequency capability, it needs code re-development like re-dividing pipeline for workload balance at each stage. And for some protocol, one chip may need to support several speed, like DDR from 666 to 2066, even higher. So for low speed support, the cycle is not fully used by the computation logic.

So for minimizing the leakage power and also with the die economic consumption, a synthesis method with time division multiplex logic sharing is proposed to fully leverage frequency capability of particular technology node without any code re-development work in this disclosure.


In the current integrated circuits designdigital chip design, almost all logic a lot of function are made by operations like such as ADD / SUB / COMPARE / COUNT, and even more basic operation like AND /NOR/XOR.


Via logic function extraction and analysis, some basic operations can be time division shared between different data paths.


Time division multiplex technique could be used during synthesis with no need to know the detailed logic structures to achieve the maximum resource utilization. In other words, this is more like a structure based method regardless the data paths' function.


Timing closure is also considered during logic share planning.


Via logic gate sharing, die size is minimized have the ability to share the same module at the gate level to minimize the resource consumption and the circuits area also with the smallest leakage power.


For the design required to support large range of speed like DDR, dynamic logic sharing can be implemented for different application speeds.

1


Page 02 of 7


Main Flow

101

102

103

104

105

106

Get a logic compiled and device mapped netlist

 Run zero wireload timing and initial placement if the synthesis tool incorporate physical optimization feature

Choose exclusive register pairs which have direct logic relationship above specific slack threshold and within

distance limit if synthesis tool is physical aware

Extract combinational logic cells between the regis...