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Package Counter-warpage during Thermal Processing to Reduce Package Warpage

IP.com Disclosure Number: IPCOM000235563D
Publication Date: 2014-Mar-10
Document File: 4 page(s) / 207K

Publishing Venue

The IP.com Prior Art Database

Abstract

By counter-warping a flip chip semiconductor package substrate during package assembly processes requiring elevated temperatures (reflow, bake, etc.), it is possible to reduce the post-processing/final warpage and flip chip interconnect stress. This can be accomplished by adding a pallet top-plate that is matted to the existing FC package assembly processing pallet design that restricts the package substrate from its natural tendency to warp/bow during thermal processing. Once thermal processing is complete, the package is removed from the process pallet and assumes its free state.

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Package Counter-warpage during Thermal Processing to Reduce Package Warpage

Abstract

By counter-warping a flip chip semiconductor package substrate during package assembly processes requiring elevated temperatures (reflow, bake, etc.), it is possible to reduce the post-processing/final warpage and flip chip interconnect stress. This can be accomplished by adding a pallet top-plate that is matted to the existing FC package assembly processing pallet design that restricts the package substrate from its natural tendency to warp/bow during thermal processing. Once thermal processing is complete, the package is removed from the process pallet and assumes its free state.

Currently, the thermal processing pallet is simply a metal carrier that allows the substrate to freely bend at any point during thermal processing. For this example, the die attach reflow process will be examined (see Figure 1). After the die is placed onto the die cage area of the substrate, the entire package is sent through a reflow oven with sections of varying temperature. The purpose of this step is to heat the bump and solder paste above their melting points (Tm) so they will melt, resulting in a good bond between the die and substrate. During this process, both the die and substrate elongate according to their coefficients of thermal expansion (CTE). For organic substrates, the CTE is much higher than that of the silicon die. After sufficient dwell time above the Tm, the package is allowed to cool. During which time, the die and substrate attempt to retract back to their original, room-temperature dimensions. However, since the substrate is now bound to the die under the die cage area, it cannot contract back to its natural length on the FC side while the BGA side is free to do so. This length difference results in the substrate warping. This creates stress on the die and bumps (particularly the outer bumps) which results in large-scale delamination within the die or localized delamination under a bump (ghost/white bumps).

With such serious, warpage-enduced failure mechanisms, much focus has been allocated toward elimination of package warpage, especially i...