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Robust Highly Configurable Power Management Unit Architecture

IP.com Disclosure Number: IPCOM000235566D
Publication Date: 2014-Mar-10
Document File: 5 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

A typical power management controller (PMC ) has many sub blocks and operation modes, which has led to a high level of complexity of digital logic in PMCs and their interactions with analog components as well as the rest of an SOC (system on chip ). Existing PMC design flow relies heavily on custom digital logic design, which can lead to many bugs. In this paper, we present a structured way to move this huge and complex custom digital logic in to standard digital logic design flow using a new isolated voltage domain and associated control circuit.

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Robust Highly Configurable Power Management Unit Architecture

Abstract

A typical power management controller  (PMC ) has many sub blocks and operation modes, which has led to a  high level of complexity of digital logic in PMCs and their interactions with analog components as well as the rest of an SOC (system on chip ).  Existing PMC design flow relies heavily on custom digital logic design, which can lead to many bugs.  In this paper, we present a structured way to move this huge and complex custom digital logic in to standard digital logic design flow using a new isolated voltage domain and associated control circuit.

 Existing PMC’s Architecture and design issues

Existing PMC’s are becoming very complex due to complex boot protocol and multiple regulators, voltage monitors and power modes.  PMC’s have a large number of signals interacting with the SOC and hence its integration in SOC requires thorough testing.  In existing designs this testing relies heavily on PMC behavioral codes for most of the design period that in almost all cases does not exactly capture what is actually implemented in the final circuit.  Huge custom digital logic in PMC is scattered and tested only for the use case, thus it leaves a chance for a lot a bugs due to low coverage of test cases.

Figure 1 shows what the various sub blocks of PMC and SOC and their integration.  It also shows typical voltage levels on which these sub blocks operate.  Most of the logic in existing PMC’s is scattered across the entire PMC more over this logic is mostly high voltage custom blocks.  Due to non standard design flow and testing this digital logic contains a lot of bugs, which are hard to find and test.

Figure 1:  Various voltage domains and sub blocks of PMC and its integration with SOC

Figure 2: Detailed diagram showing various voltage domains and sub blocks of PMC

In Figure 2, an example PMC boot sequence is shown.  Here it is assumed that most of scattered digital logic of PMC is now placed inside one block, which is marked to come alive at time T0.  Time T0 is when SOC HV supply starts to ramp up.

Figure 3:  Improvised PMC architecture with new isolate voltage

Figure 3 shows an improvised design developed to address the various issues discussed above.  This PMC architecture...