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A Novel Approach For Verification of Pipeline Flops in an SoC

IP.com Disclosure Number: IPCOM000235567D
Publication Date: 2014-Mar-10
Document File: 6 page(s) / 908K

Publishing Venue

The IP.com Prior Art Database

Abstract

In any SoC (System on Chip), in order to meet timing across critical paths, there is a need to add pipeline flops (also called repeater flops) across these paths. Depending upon the timing criticality of the paths, there can be different number of pipeline flop stages in a particular path. There can be thousands of such paths in a design where pipeline flops are inserted. There is currently no clear strategy to verify the issues associated with pipeline flops insertion. STA (Static Timing Analysis) would only find the timing aspect of the pipelines and not the functional aspect. Functional simulations are not comprehensive enough to expose pipeline issues. This paper explains a methodology to verify various issues encountered with pipeline insertion. This methodology is parameterized to verify different number of pipeline stages and can be seamlessly integrated into the already existing functional regression suite, thereby leveraging the already existing functional verification infrastructure to catch pipeline issues.

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TITLE 

A Novel Approach For Verification of Pipeline Flops in an SoC.

ABSTRACT

In any SoC (System on Chip), in order to meet timing across critical paths, there is a need to add pipeline flops (also called repeater flops) across these paths. Depending upon the timing criticality of the paths, there can be different number of pipeline flop stages in a particular path. There can be thousands of such paths in a design where pipeline flops are inserted. There is currently no clear strategy to verify the issues associated with pipeline flops insertion. STA (Static Timing Analysis) would only find the timing aspect of the pipelines and not the functional aspect. Functional simulations are not comprehensive enough to expose pipeline issues. This paper explains a methodology to verify various issues encountered with pipeline insertion. This methodology is parameterized to verify different number of pipeline stages and can be seamlessly integrated into the already existing functional regression suite, thereby leveraging the already existing functional verification infrastructure to catch pipeline issues.

INTRODUCTION

In any SoC, it is a common practice to insert a number of pipeline flops (also called repeater flops), in timing critical paths. The timing criticality in the design can be due to different reasons, namely, physical distance, high frequency, signals crossing different voltage domains etc. With increasing size and complexity of SoCs, there can be thousands of such timing critical paths in the design, which need pipeline stages.

There are a number of challenges associated with verification of pipelines-

•       No clear strategy for pipeline connectivity verification.

•       Current methodology relies on functional test suite which is not comprehensive to expose pipeline issues.

•       Static timing analysis tools just look at the timing aspect and are not equipped to find functional/connectivity issues associated with the pipelines.

PIPELINE ISSUES

Figure-1 shows a case where, in order to meet timing on a signal crossing different voltage domains (VDDA -> VDDB), two-stage pipeline flops(PIPE A, PIPE B) are added in the path (SigA -> SigB).

Figure-1: Two-Stage Pipeline Path

If the pipelines are perfect, a single clock pulse at the IPA output (IPA->SigA)

•       Will reach the first pipeline output(PIPE A->QA) after 1 clock(CLKA)

•       Will reach the destination input(IPB->SigB) after 2 clocks(CLKA)

Figure-2 shows the pipeline issues. Due to these issues, the timing of propagation of pulses across the source to destination will be different as...