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METHOD TO CONTROL CGC CLOCK INPUT FOR LOW POWER MODE SWITCH

IP.com Disclosure Number: IPCOM000235568D
Publication Date: 2014-Mar-10
Document File: 3 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Low power design is increasingly important in SOC designs. The most effective way of low power design is cutting off the power of unused power domains. Also the clock gating cell (CGC) is another important tool of low power design. These two features are implemented on almost every low power SOC design. Then the CGC power down and power up behavior will be in almost all very low power design chips.

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method to control CGC clock input for low power mode switch

Low power design is increasingly important in SOC designs.  The most effective way of low power design is cutting off the power of unused power domains.  Also the clock gating cell (CGC) is another important tool of low power design.  These two features are implemented on almost every low power SOC design.  Then the CGC power down and power up behavior will be in almost all very low power design chips.

What its behavior will be like?

Let’s first remind how CGC works in normal power case. FIG. 1 shows a CGC structure.

FIG. 1 CGC structure

And FIG. 2 shows the truth table for the CGC of FIG. 1.

clock

gate

Qint

 

Qint

clock

gating clock

0

0

0

1

1

1

0

1

1

0

-

0

1

-

Qint

-

0

0

FIG. 2 CGC Truth Table

From FIGS. 1 and 2 we can get one key feature of CGC is that when clock input is 1, no matter if the gate input is toggling or not, CGC output will be maintained and the value is the gate input value at the clock positive edge.  This key feature can prevent positive clock pulse being cut partly.  However, if we use CGC in power off domain, let’s see how it works when power up.

FIG. 3 CGC in power-off domain

Before the positive edge of VDDOK, because power is still not supplied, then the gate value is X.  This X will be sampled by CGC because clock positive edge (change from X to 1) is coming at the same time.  This X output at gating clock will be maintained until clock is changing to low.  So clock input half cycle high at...