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MECHANISM TO AVOID VOLTAGE OVERSHOOT/UNDERSHOOT DURING DYNAMIC FREQUENCY SCALING

IP.com Disclosure Number: IPCOM000235571D
Publication Date: 2014-Mar-10
Document File: 3 page(s) / 163K

Publishing Venue

The IP.com Prior Art Database

Abstract

Dynamic frequency scaling (DFS) has become a key power saving technique in SOCs. Also, there has been an increase in chips supporting multiple external interfaces such as USB, ENET and high frequency operating cores. There is a need to scale down core and system frequencies, which include system RAM and flash frequencies while keeping the interfaces at constant frequency. To maintain the baud clock there is always a restriction on the system frequency side to have minimum required bandwidth. An SoC supporting DFS may be required to change multiple clock ratios along with various handshaking within the SoC and also ensure that external transfers are not impacted. During this frequency shift, a voltage overshoot or undershoot can occur. Traditionally, it is handled by scaling the frequencies in steps, which may cause a moment when the system clocks become asynchronous. For example, core and switch fabric is working at 160MHz and USB system bus at 80MHZ as there is a restriction that USB system side frequency should be >=60MHZ to support ULPI @480Mbps and DFS is requested. Scaling core frequency to 40MHz may immediately cause an overshoot if it is done instantaneously. If it is done in steps of 40 as in 160->120->80->40, there will be duration when switch fabric is at 120 and USB at 80 making them asynchronous, which may not be supported by SoC and ongoing transaction may be corrupted. In this paper, we propose how to prevent such voltage over and under shoot using counter based controls and voltage monitoring signals.

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Mechanism to avoid voltage overshoot/undershoot during dynamic frequency scaling

Abstract 

Dynamic frequency scaling (DFS) has become a key power saving technique in SOCs.  Also, there has been an increase in chips supporting multiple external interfaces such as USB, ENET and high frequency operating cores.  There is a need to scale down core and system frequencies, which include system RAM and flash frequencies while keeping the interfaces at constant frequency.  To maintain the baud clock there is always a restriction on the system frequency side to have minimum required bandwidth.  An SoC supporting DFS may be required to change multiple clock ratios along with various handshaking within the SoC and also ensure that external transfers are not impacted.  During this frequency shift, a voltage overshoot or undershoot can occur.  Traditionally, it is handled by scaling the frequencies in steps, which may cause a moment when the system clocks become asynchronous.  For example, core and switch fabric is working at 160MHz and USB system bus at 80MHZ as there is a restriction that USB system side frequency should be >=60MHZ to support ULPI @480Mbps and DFS is requested.  Scaling core frequency to 40MHz may immediately cause an overshoot if it is done instantaneously.  If it is done in steps of 40 as in 160->120->80->40, there will be duration when switch fabric is at 120 and USB at 80 making them asynchronous, which may not be supported by SoC and ongoing transaction may be corrupted.  In this paper, we propose how to prevent such voltage over and under shoot using counter based controls and voltage monitoring signals.

Problem Definition

•      Not easy to estimate to load current changes in a system where we are supporting dynamic frequency scaling or switching between different run power modes.

•      It is d...