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Area Optimized Matched Layout for Multi-finger and Cascode Transistor for Analog Applications

IP.com Disclosure Number: IPCOM000235656D
Publication Date: 2014-Mar-18
Document File: 9 page(s) / 3M

Publishing Venue

The IP.com Prior Art Database

Abstract

In Analog circuit design, often large transistors are used to satisfy various design requirements (high gain or low mismatches, etc.). Usually these transistors are implemented by parallel combinations of transistors of the same width and hence known as multiplier or m-factor. Another method to implement these transistors is by breaking the gate in multiple gates and sharing the source and drain and hence known multi-finger approach. These two methods can be used separately or in combination.

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Area Optimized Matched Layout for Multi-finger and Cascode Transistor for Analog Applications

1.    Introduction

In Analog circuit design, often large transistors are used to satisfy various design requirements (high gain or low mismatches, etc.). Usually these transistors are implemented by parallel combinations of transistors of the same width and hence known as multiplier or m-factor.  Another method to implement these transistors is by breaking the gate in multiple gates and sharing the source and drain and hence known multi-finger approach.  These two methods can be used separately or in combination.

As CMOS VLSI technology shrinks,transistor size is being limited by the maximum allowed poly area.  For example, in TSMC 28nm technology, the maximum gate poly area should be less than 0.3 um2.  For analog circuits, most of the layout is made up of matching patterns (which is also known as common centroid pattern) of transistors having large equivalent width and length.  Generally such big transistors are realized by making multiple and multi-finger to save area and reduce variation due to manufacturing gradient.  Sometimes circuits need a cascode architecture for high gain/noise isolation so there is room for improvement because of poly area limitation.

To overcome this poly area limitation and to save layout area, we propose a method for generating matched layouts having matching pairs of multi-finger /cascode structure in analog design.  This will help save layout effort/time and area.

2.    Proposed Architecture Description

a.    flow Chart and various steps

In figure 1, a flow chart of the proposed scheme is given.

Figure 1 - Flow chart

In step 1, unit cell of the matched pattern must be identified. This unit cell may have the more than one finger. So there are two possibilities:

a.) When the numbers of fingers are odd as shown in Figure 2   

b.) When the number of fingers are even as shown in Figure 3.

Figure 2 - Unit Cell for Multi-finger Transistor (Odd fingers)

Figure 3 - Unit Cell for Multi-finger Transistor (Even fingers)

In case of cascode transistors, the unit cell can be as shown in Figure 4.

Figure 4 - Unit Cell for Cascode Transistor

In step 2, equivalent transistor of unit cell from step1 needs to be determined. This equivalent transistor (on right side of Figure 5) would have the outer geometry similar to our unit cell (on left side of Figure 5) as shown in Figure 5.

Figure 5 - Unit Cell for multi finger and it’s equivalent Transistor

In step 3, common centroid layout with equivalent transistor will be generated using any of the methods available to generate common centroid layout of multiple but single finger transistors. The discussion of layout generation method and optimized placement scheme is not a part of this paper.

In step 4, the equivalent transistor will be replaced by an actual unit cell. Since the outer geometry of both equivalent transistor and unit cell are the same, there will be no missing connection or ...