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IO Supply Power Switch

IP.com Disclosure Number: IPCOM000235657D
Publication Date: 2014-Mar-18
Document File: 6 page(s) / 141K

Publishing Venue

The IP.com Prior Art Database

Abstract

An effective use of voltage islands for meeting SoC power and performance requirements, while maintaining time to market requires can be challenging. Due to the rising functionality and increasing complexity, power dissipation has become a critical design constraint for System on Chip (SoC). Power gating and voltage scaling play a vital role in power reduction in sub-90nm low power designs. Power gating enables sleep mode by turning off power supplies to inactive blocks through switch cells. The basic power gating strategy is to provide two power modes: a low power mode and an active mode. The goal remains to optimize switching timing between the two modes to ensure maximum power savings with minimal performance impact. In this paper, we propose a power gating approach to turning off of various IO supply banks, which enables power savings during standby and other low power modes while maintaining the same performance in active mode. Low power design techniques often focus exclusively on the internal gates power reduction, while sidelining the fact that IO cells in the SoC also result in signification amounts of power consumption. The need to drive large pad capacitances and board traces translates to increases in IO power consumption. Leakage is also one of most critical power component for IO cells, which tend to leak more relative to standard cells due to presence of components like termination resistors, pull ups, pull downs, etc.

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IO Supply Power Switch

Abstract

An effective use of voltage islands for meeting SoC power and performance requirements, while maintaining time to market requires can be challenging.  Due to the rising functionality and increasing complexity, power dissipation has become a critical design constraint for System on Chip (SoC).

Power gating and voltage scaling play a vital role in power reduction in sub-90nm low power designs. Power gating enables sleep mode by turning off power supplies to inactive blocks through switch cells.  The basic power gating strategy is to provide two power modes: a low power mode and an active mode.  The goal remains to optimize switching timing between the two modes to ensure maximum power savings with minimal performance impact.

In this paper, we propose a power gating approach to turning off of various IO supply banks, which enables power savings during standby and other low power modes while maintaining the same performance in active mode.  Low power design techniques often focus exclusively on the internal gates power reduction, while sidelining the fact that IO cells in the SoC also result in signification amounts of power consumption.  The need to drive large pad capacitances and board traces translates to increases in IO power consumption.  Leakage is also one of most critical power component for IO cells, which tend to leak more relative to standard cells due to presence of components like termination resistors, pull ups, pull downs, etc.

Problem Definition

All chips communicate with the outside world in some manner.  Signals flow onto and off a chip, and the chip needs to receive power.  For lead frame based packages, chip or die pads are electrically connected to fingers of the metal lead frame with bond wires.  The portions of the lead frame fingers that extend or are exposed at the outside of the package are the package pins.  In pad ring design, there may be different banks depending on various interfaces involved in the SOC.  By bank, we mean a segment in the pad ring that has IO cells that operate at the same voltage.  Interfaces working at different voltages need to be placed in different pad ring banks, whereas interfaces working on the same voltage value but belonging to different interfaces can be grouped together, as discussed below.  Each IO bank in the pad ring has its own power supply while the ground is shared between them.

With ever rising chip functionality, limitations in power and pin count are challenging designers.  As technology scales down, more and more functionality is being implemented on the SOC. This is in turn resulting in rising pin counts needed at the SOC.

One reason that interfaces in general have been moving from parallel to serial is the need to reduce the number of I/O pads.  DDR3 I/Os consume the greatest number of pads.  Other parallel interface examples include Flash Interface, Ethernet, MII, etc. These I/Os constrain the floor plan since they must be opt...