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Method and System for Providing a Low Power and Low Jitter Multiphase Clock Distribution

IP.com Disclosure Number: IPCOM000235761D
Publication Date: 2014-Mar-25
Document File: 4 page(s) / 92K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for implementing a multiphase clock distribution system where clocks are distributed using current mode buffers. The clock distribution may distribute all phases of a divided clock at a half rate clocking scheme. Additionally, the clock distribution involves full rate clock schemes where a full rate clock is distributed to a far end of a transmission line and is locally divided using a clock divider to generate multiphase half rate clocks.

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Method and System for Providing a Low Power and Low Jitter Multiphase Clock Distribution

The continued scaling of semiconductor technology has led to colossal increase (multi-gigahertz range) of on-chip processing rate. The ever increasing data/clock rates due to scaling, time restricted precision is dependent on inevitable use of phase/delay locked loops and extensively degrades the link performance. Variation in the timing of a bit transition relative to an ideal clock is called jitter. Jitter reduces width of the data eye. In such constrained environment, jitter deteriorates performance of a High Speed Serialization Deserialization (HSS) link significantly. Moreover, jitter issue may give serious problem for distribution of multiple phases of clock in the network. Additionally, one more problem in HSS is that a significant amount of total real time power is dissipated in conventional buffer driven clock distribution network. High clock rates make the task even more challenging.

Disclosed is a method and system for implementing a multiphase clock distribution system where clocks are distributed using current mode buffers. The clock distribution may distribute all phases of a divided clock at a half rate clocking scheme. Additionally, the clock distribution involves full rate clock schemes where a full rate clock is distributed to a far end of a transmission line and is locally divided using a clock divider to generate multiphase half rate clocks.

In accordance with the method, architecture to be used in HSS cores for data transmission is illustrated in Fig. 1.

Figure 1

Data transmission is performed at 15G using 7.5 GHz clock for chip to chip link. Four phases of C 2 clocks (7.5 GHz) are distributed using Complementary Metal Oxide Semiconductor (CMOS) buffers across a 2 mm Transmission Line (TL). The clocks are boosted CMOS buffers to regain the amplitude loss incurred by the TL.

The architecture illustrated in Fig. 1 is modified to obtain lesser power consumption and less jitter by using a half rate clocking scheme as illustrated in Fig. 2.

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Figure 2

The architecture includes a Phase Locked Loop (PLL) clock that is divided by two and all four phases of the divided PLL clock are distributed to the load using current mode buffers. The buffers are configured as open drain buffers with resistive termination at a far end of the TL. The value of the resistance and the current in the tail current source of the open drain buffer...