Browse Prior Art Database

A Novel Best-in-Class De-Compression technique that generates pseudo-randomness utilizing clock gating and other control's for sequential elements.

IP.com Disclosure Number: IPCOM000235762D
Publication Date: 2014-Mar-25
Document File: 6 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

Compression is a technique used for reducing the manufacturing test data volume, test application time and use of minimum pins to adapt ATPG to enable multisite-testing. It is a combination of DFT hardware structures and associated ATPG capabilities via EDA tools that make this a reality. The use of data compression can address the data volume and the pin counting issues without sacrificing test coverage and quality of test. The EDA ATPG tools create compressed stimulus patterns which will be stored in the ATE and these patterns will be applied to the Design under Test. By Implementing the Compression techniques, multi-fold reduction in tester scan buffer data could be achieved. Aliasing / Correlation issues, Higher IR drop and high usage of the Test pins are the main problems in the current compression techniques. There are multiple Compression techniques that have been used in the industry utilizing several different architectures OPMISR Illinois and XOR Compression are the standard ones. And each one deals with different problem’s separately with several limitations / compromises. The present disclosure depicts a new compression technique which could be seen as an enhanced version of the current compression techniques but overshadowing them in terms of compression ratio, lower IR drop and eliminating the need of several Test pins which are the limitations of the present compression techniques. The current compression architecture has been exploited with the addition of more pipe stages and ICG (clock gate cells) gates, yielding out a concept of virtual PI’s which will help in eradicating the need of many test pins , as well as will increase the compression ratio . Last but not the least, this technique would be more power aware since IR drop by architecture is minimized.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 40% of the total text.

Page 01 of 6

A Novel Best-in-Class De-Compression technique that generates pseudo -randomness utilizing clock gating and other control 's for sequential elements.

The novel idea of providing more robustness to the current compression technology in terms of power and more importantly usage of test pins makes the following claim

"A Novel Best in Class Asymmetric/Symmetric De-Compression / Compression technique that utilizes sequential control's "

Basic operation of Compression based DFT-ATPG (shown in Fig 1).


 EDA ATPG tools generate pattern stimulus based on the compressor de-compressor structures embedded in the design. These patterns are applied to the Design under Test.


 The test data pass through De-compressor logic (Spreader) in the Design, Where the test data is expanded / spread to multiple channels. Multiple techniques are adopted in industry to achieve spreading / de-compression. Most common ones for spreading / De-compression are XOR with and without pipe stages, Combinational gates with and without pipe stages, MISR, Illinois, Sequential Illinois, LFSR to name a few.

1


Page 02 of 6

2


Page 03 of 6


 The test data which is spread is shifted though internal scan stumps / channels until all the flops are initialized.


 The design is then placed in Scan capture mode and is used to detect faults in the design.


 Resultant data of capture mode is then shifted out sequentially to compactor logic (Compressor) though the same scan stumps / channels.


 Compactor takes the stream of data from stumps and translate's the data to compressed data. The most common compressor structures used in the industry are XOR, MISR, LFSR based to name a few.

Prior art:

Fig 2 is an extension of the basic architecture shown in Fig 1 and is popularly used in multisite-testing where there are very few scan pins available to contact. A master scan chain is used to scan in data which operates at multiples of scan rate. In the figure, one master chain feeds 4 internal scan channels and operates at a scan rate of 4 times the scan rate of the device under test.

Fig 3 shows a sequential encoding technique where the master chain has tap-points that feed into XORs to generate many virtual PIs.

Few of the common problems of these structures are listed below.

Illinois and sequentially encoded Illinois compression techniques suffer from correlation issue which is, since the same data gets applied at a given cycle to multiple stumps and hence multiple sequential elements, By design if the flop expects different control value on the set of flops, Then this cannot be achieved, And hence might result in loss of coverage. Also ATPG tools when targeting multiple faults in a pattern, if control care bits land up in same scan pin with flipped values, Then since the tool cannot achieve this, tool would have to target these 2 faults in different patterns which might inflate pattern count.

XOR with/without pipe stages LFSR and MISR based de-compression techniques face chal...