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Aging compensation Using a Dual Gate LDMOS

IP.com Disclosure Number: IPCOM000235763D
Publication Date: 2014-Mar-25
Document File: 2 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

A dual gate lateral double-diffused MOSFET (DGLDMOS) and a method for aging compensation in a High Voltage Metal Oxide Semiconductor (HVMOS) device is disclosed.

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Aging compensation Using a Dual Gate LDMOS

Disclosed is a dual gate lateral double-diffused MOSFET (DGLDMOS) and a method for aging compensation in a High Voltage Metal Oxide Semiconductor (HVMOS) device.

In an implementation, the DGLDMOS used is developed using the Fully Depleted Silicon on Insulator (FDSOI) technology.

Fig. 1 is an illustration of a structure of the DGLDMOS integrated on a bulk wafer with a gate stack.

Figure 1

The DGLDMOS gate stack can be composed of one of, but not limited to, a polysilicon gate, a metal gate such as a TiN or a TiAlN gate, and a multilayer gate comprising a polysilicon gate and a metal gate. In case of a multilayer gate stack, the polysilicon layer can be on top of the TiN layer. In addition, the gate stack can include an oxide layer composed of one of, but not limited to, a single layer and a multilayer of dielectrics such as SiO2, HfO2, HfSiON, and HfSiO2. Further, the oxide layer of the gate stack can be composed of an HfSiON on top of a SiO2 interfacial layer.

As illustrated in Fig.1, the DGLDMOS includes a second control gate (G2) which is situated in a "drift region" between a first gate and a drain of the DGLDMOS. The method monitors the second control gate (G2) to compensate drift/variation in operation of the DGLDMOS due to aging.

In an embodiment, the method detects aging, when ON state current or any characteristics of the HVMOS device is either outside lower or upper limits defined by a designer.

In another embo...