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Structures reducing wafer bowing

IP.com Disclosure Number: IPCOM000235766D
Publication Date: 2014-Mar-25
Document File: 2 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a Back End of Line (BEOL) structure with particular mechanical strength to effectively reduce the warping of wafers.

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Structures reducing wafer bowing

In the stacked chip process, wafers need be thinned to 50um-200um thick for regular 300mm Silicon (Si) wafers. The Coefficient of Thermal Expansion (CTE) mismatch of different films on chips and temperature cycles during the semiconductor process causes significant wafer bowing, which becomes more significant for thin wafers. Handling and processing thin wafers becomes extremely challenging. A method is needed to reduce the wafer bowing.

The novel contribution is a specific Back End of Line (BEOL) structure with particular mechanical strength to effectively reduce the warping of wafers. This structure can be fabricated by regular BEOL process and requires no additional process or masks.

Figure: Examples of reinforced segment

[Below, showing Through-Silicon Vias (TSV)]

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