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Special Construct Coordinate Business process for GR violation or defect PFA in TEG

IP.com Disclosure Number: IPCOM000235767D
Publication Date: 2014-Mar-25
Document File: 3 page(s) / 55K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to generate a list of special pattern layout within a chiplet/TEG and output the results into a spreadsheet.

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This is the abbreviated version, containing approximately 67% of the total text.

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Special Construct Coordinate Business process for GR violation or defect PFA in TEG

The verification of special constructs (SCs) on the hardware is one of the essential steps for the product yield. In addition to the validation macro, the inline measurement of SCs in the chip design provides an SC validation in real design surroundings. However, allocating the exact location is difficult because the construct cell name might not be included in the final chip design and the hierarchy can be varied by designers.

A method is needed to provide the integration team with a list of SC coordinates within the chip for inline verification.

The novel contribution is a workflow to generate a list of SCs within a chiplet/TEG (chiplet with technology content) and output the results into a spreadsheet. This approach requires no additional SC searching code, as it utilizes the existing design rule check (DRC). The output SC list can be adjusted by users, using a definable input SC name. This process enables easy searching via pull-down filter for each SC name. The output file can be directly input to a measurement tool to automatically allocate the interested analysis structure on wafer. This methodology and process can be applied to different technology nodes.

This new process provides a complete list of SC per TEG in each test site in a matter of less than a hour for Physical Failure Analysis (PFA) compared to a previous search cycle in which the process takes a long time to...