Browse Prior Art Database

Method for Integrating Dual-Epitaxy with Equivalent Junction Overlap

IP.com Disclosure Number: IPCOM000235768D
Publication Date: 2014-Mar-25
Document File: 4 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for integrating dual-epitaxy with equivalent junction overlap. The method includes undercutting Source/Drain (S/D) region in a device polarity to compensate for a difference in spacer thickness.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 99% of the total text.

Page 01 of 4

Method for Integrating Dual-Epitaxy with Equivalent Junction Overlap
Disclosed is a method for integrating dual-epitaxy with equivalent junction overlap. The method includes undercutting Source/Drain (S/D) region in a device polarity to compensate for a difference in spacer thickness.

In accordance with the method, fins and gate stack are formed on two devices as illustrated in Fig. 1.

Figure 1

A Spacer dielectric is deposited on the fin and gate stack as illustrated in Fig. 2.

Figure 2

The spacer is formed on first device polarity and the second device polarity is covered with a mask as illustrated in Fig. 3.

1


Page 02 of 4

Figure 3

Thereafter, an expitaxy is formed on polarity of first device as illustrated in Fig. 4.

Figure 4

Another spacer dielectric is deposited on top of the epitaxy on the first device as illustrated in Fig. 5.

Figure 5

A thicker spacer is formed on the second device and the polarity of the first device is covered with a mask as illustrated in Fig. 6.

2


Page 03 of 4

Figure 6

Fins on the second device polarity are fully recessed in the S/D region and optionally recessed in Silicon on Insulator (SOI) region as illustrated in Fig. 7.

Figure 7

The fins on the second device polarity are undercut using cyclic wet oxidation and etching as illustrated in Fig. 8.

Figure 8

3


Page 04 of 4

Thereafter, epitaxy is formed on second device polarity as illustrated in Fig. 9.

Figure 9

Thus, the method disclosed herein integrates dual epitaxy with equivalent...