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FinFETs with multiple fin heights

IP.com Disclosure Number: IPCOM000235771D
Publication Date: 2014-Mar-25
Document File: 4 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to combine the advantages of both the bulk and Semiconductor on Insulator (SOI) approaches to multiple fin heights in order to economically form Fin Field Effect Transistors (FinFETs) of variable fin height (Hfin).

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FinFETs with multiple fin heights

A method is needed to economically form Fin Field Effect Transistors (FinFETs) of variable fin height (Hfin). At each successive Complimentary Metal-Oxide Semiconductor (CMOS) technology node, the nominal active region (RX) width is scaled down as part of the effort to reduce the total circuit capacitance. In a FinFET technology, this corresponds to reducing the number of fins per RX island (nfin). Eventually, the process reaches a point where the nominal nfin = 1 and, thus, no further nfin scaling is possible. Hfin scaling is one way to address this. However, in practice, some circuits may need a larger Hfin to achieve high drive current, while other circuits may need small Hfin to keep capacitance low, while still other circuits may require a combination of tall Hfin and short Hfin (e.g., to optimize the NFET-to-PFET beta ratio, such as in Static Random Access Memory (SRAM)).

In a known solution to this problem, bulk FinFETs of differing Hfin are formed by using a different fin reveal etch for each Hfin that is desired. The problem here is that, since these are bulk FinFETs, for each different Hfin the punchthrough stopper (PTS) implants must be tuned so that the PTS peak location is just below the active fin. Thus, for each added Hfin value, an additional PTS implant must be added/tuned.

An alternative approach is to fabricate fins of different heights on Semiconductor on Insulator (SOI). This avoids the requirement for PTS implants, but is accomplished by cutting from the top of the fin to achieve different Hfin values (i.e. the bottoms of all fins are co-planar, but the tops are not). This leads to downstream integration challenges for the gate stack, which now has...