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Method of applying a callback mechanism to enable correct processing of complex order dependent constraints.

IP.com Disclosure Number: IPCOM000235772D
Publication Date: 2014-Mar-25
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a system and method for performing static timing analysis of digital integrated circuit wherein timing constraints for at least one first timing point are dependent on computed timing data for at least one second timing point. The second timing point is upstream of the first timing point. Callbacks are used to query timing data at the second timing point during the application of timing constraints at the first timing point.

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Method of applying a callback mechanism to enable correct processing of complex order dependent constraints.

Usage of hierarchical design methodologies enables teams to re-use the same functional block on the chip many times. While internal parts of such blocks can be analyzed somewhat independently of the environment in which the blocks are to be used, the boundary of the blocks relies on the in-context environment seen by each macro instance for correct analysis. This in-context environment can be significantly different and constraints for timing analysis of the boundary logic of such blocks needs to be appropriately adapted to ensure working hardware. This can be done through asserting a superset of constraints during block timing analysis, which results in runtime penalty, increased memory use during analysis, and potentially significant overhead of maintaining associated timing constraints.

Another approach is to map timing assertions used in the original analysis to the exact timing environment seen by each unique instance of the block in-context. This approach, however, requires precise ordering of constraint loading for all the blocks in the system, since the constraint mapping technique relies on the presence of valid input data. Due to the complex structure of the hierarchical design blocks, achieving such ordering is not practical and simply ordering blocks based on input/output relationships can cause circular dependencies.

The solution is a novel application of a callback mechanism operating with levelized order processing to correctly apply timing constraints with order dependency. One such application is in timing multiple instances of hierarchical blocks. This method can be used during deterministic or statistical timing analysis of designs containing hierarchical macros, in order to avoid error prone definition of inter-block dependencies or alternative g...