A Method and System for Providing a High-k Metal Gate Structure with Graphene Liner
Publication Date: 2014-Mar-25
The IP.com Prior Art Database
A method and system is disclosed for providing a metal gate stack comprising a combination of metals and a graphene liner material existing preferentially between the metal gate stack and surrounding insulator materials such as, but not limited to, gate dielectric layers and sidewall spacers.
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A Method and System for Providing a High -k Metal Gate Structure with Graphene Liner
Gate length scaling increases gate sheet resistance due to smaller cross-sectional gate area. As gate lengths are scaled down, gate resistance increases, which impacts circuit delay. The circuit delay is exacerbated as the gate length becomes small enough such that only workfunction metals can fit within the gate stack, thus pinching off the gate stack to prevent filling of a low-resistance metal. The problem is partially addressed by increasing gate height, which reduces gate sheet resistance. However, due to increase in gate height, a parasitic capacitance penalty is imposed while also increasing vertical gate resistance.
Disclosed is a method and system that provides a metal gate stack comprising of combination of metals and a graphene liner material existing preferentially between the metal gate stack and surrounding insulator materials such as, but not limited to, gate dielectric layers and sidewall spacers. The method and system incorporates the graphene liner material inside a High-k Metal Gate (HKMG) stack before deposition of the metal gate stack, to provide a low-resistance path around the perimeter of the gate. The graphene liner material preferably exists between the high-k dielectric and workfunction metals such as, but not limited to, TiN and TiC. Graphene has a very low resistivity in comparison to the workfunction metals in the RMG stack and as a monolayer material graphene can fit inside a small gate opening without impacting the workfunction metal fill.
In an embodiment, the graphene liner exists only along sidewalls as shown in fig. 1.
During integration of graphene in the metal gate stack a "gate-first" process flow is
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utilized, wherein the gate stack is heavily doped SiC (n-type or p-type). Alternatively, and preferably, a gate-las...