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Method and Structure for Forming Dielectric Isolated Bulk Fins with Arbitrary Dielectric Isolation Thickness

IP.com Disclosure Number: IPCOM000235780D
Publication Date: 2014-Mar-25
Document File: 5 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use multiple sacrificial Siege layers sandwiched between n+ silicon layers (or SiGe with lower percentage of Ge) to form arbitrary dielectric isolation thickness for a bulk Fin Field Effect Transistor (FinFET). The lower percentage of Ge regions act as a buffer to the higher percentage of Ge regions, and this low-Ge/high-Ge stack can be repeated to make a sacrificial region that is arbitrarily thick.

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Method and Structure for Forming Dielectric Isolated Bulk Fins with Arbitrary Dielectric Isolation Thickness

This solution addresses the problem of forming an arbitrary dielectric isolation thickness for a bulk Fin Field Effect Transistor (FinFET). This dielectric isolation makes it relatively simple to form embedded Dynamic Random Access Memory (eDRAM); however, forming an isolation layer that is thick enough (~150nm) to accommodate the deep trench (DT) capacitor flow is non-trivial. Using a buried oxide through silicon (BOTS) flow, this can be achieved, but this results in the formation of a fin "tail" which increases subthreshold leakage, thereby complicating device design. A silicon on nothing (SON) or SON-like flow is the main alternative, wherein a sacrificial SiGe layer exists between the fin and substrate and is selectively removed (and replaced with oxide, or left as an air gap); however, the critical thickness of this SiGe layer limits how thick the underlying oxide may be (~ 30nm). Furthermore, the dummy gate stack anchors the active fin during the sacrificial SiGe removal, so a thicker sacrificial layer also requires a taller dummy gate stack to ensure the active fin is anchored.

The novel contribution is a method to use multiple sacrificial SiGe layers sandwiched between n+ silicon layers (or SiGe with lower percentage of Ge). The lower percentage of Ge regions act as a buffer to the higher percentage of Ge regions, and this low-Ge/high-Ge stack can be repeated to make a sacrificial region that is arbitrarily thick.

The process flow is SON-like, but enables an arbitrary thickness for the sacrificial layer without requiring the dummy gate (which holds the active fin during the sacrificial layer etch) to be equally tall. Furthermore, this process flow allows different dielectric isolation thicknesses within a die. For example, eDRAM devices may have a thicker dielectric isolation to accommodate the DT process requirements, while logic devices may have a thinner dielectric isolation to accommodate perf...