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Method and System for Suppressing Bulk Punch through Leakage in Bulk FinFET

IP.com Disclosure Number: IPCOM000235781D
Publication Date: 2014-Mar-25
Document File: 5 page(s) / 119K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for suppressing bulk punch through leakage in bulk FinFET. The method and system creates a structure using a dielectric that is inserted at the bottom of the source/drain regions. The structure creates a physical barrier which limits the source/drain dopants from being so deep and allows diffusing vertically resulting in increasing the contact area and reduces contact resistance.

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Method and System for Suppressing Bulk Punch through Leakage in Bulk FinFET

Disclosed is a method and system for suppressing bulk punch through leakage in bulk FinNet. The method and system creates a structure using a dielectric that is inserted at the bottom of the source/drain regions. This structure creates a physical barrier which limits the source/drain dopants from being so deep and allows diffusing vertically. In essence, similar to a SOI FinFET, the buried insulator exists only under the source/drain regions, suppressing the leakage. The structure containing source/drain epitaxy grows laterally from channel sidewall, which in turn enables a structure to contact the full height of the active fin. This, in turn, increases contact area and reduces contact resistance.

In accordance with the method and system, as shown in the figure 1, a starting structure, the bulk fin and local trench isolation (LTI) regions are formed, followed by formation of the gate stack (or dummy gate stack in a RMG flow) and sidewall spacers. Process flow thus assumes the presence of a dummy gate stack (RMG flow), which comprises a dummy gate dielectric (oxide), a dummy gate material (polysilicon), and a capping layer (oxide). A gate-first flow may also be utilized here.

Figure 1

As shown in the figure 2, before the source/drain epitaxial growth is performed, fin recesses etch is first performed. The depth of this recess etch may be any depth, and the depth is chosen to coincide with the top surface of the LTI region.

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Figure 2

Further, a gas cluster ion beam (GCIB) implant is performed, to directionally deposit dielectric material (e.g., oxide, nitride) over the bottom portion of the recessed profile, without depositing any dielectric along the channel sidewall. Even if the fin recess etch is not perfectly anisotropic, such that some GCIB material deposits along the channel sidewall, its thickness is much lower than the dielectric thickness along the bottom. A small follow-up etch is then performed to clear the channel sidewall without completely removing the dielectric along the bottom as shown in the figure 3.

Figure 3

Next, the source/drain epitaxial regions are grown, using the...