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Method and structure to prevent epi merge related shorts between devices for finfet technology

IP.com Disclosure Number: IPCOM000235784D
Publication Date: 2014-Mar-25
Document File: 4 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure that enable the extension of a fin merge scheme to future nodes.

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Page 01 of 4

Method and structure to prevent epi merge related shorts between devices for finfet technology
For single dummy fin spacing between devices, an epitaxy (epi) merge scheme has extremely high risk of shorting. The key shorting direction is along the gate (PC). There is less risk along the fin due to tuck under.

Figure 1: Space

Figure 2:

The novel contribution is a method and structure that enables extension of a fin merge scheme to future nodes. With this structure, fins are not cut in the non-active areas. Instead, the fins are encapsulated by a dielectric material on four sides and the top. This is applicable to both Silicon on Ion (SOI) and bulk technologies.

Figure 3: Flow: Blanket Fin formation (no Fin cut)

High-k or other protective dielectric deposition needs to withstand gate and spacer etch and epitaxy precleans (e.g., hafnium oxide and other high-k materials).

Figure 4: Flow: Top view

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Page 02 of 4

Use a mask and remove high-k from active regions. The high k will not essentially render the fins inactive. No epi will grow; however, an electrical connection between two devices on the same fins needs to be resolved.

Figure 5: Flow

Ends of fins are cut and have an opening width of, for example, approximately 30nm.

Figure 6: Flow

Continue etch in the fin. Now two adjacent devices sharing the same fin are electrically isolated.

Figure 7: Flow

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Page 03 of 4

The approach can be spacer formation or even divot fill-like. The spacer formation is shown here. This p...