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FinFET spacer formation without fin damage

IP.com Disclosure Number: IPCOM000235785D
Publication Date: 2014-Mar-25
Document File: 3 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to form FinField Effect Transistors (FinFET) without fin damage. The novel approach is to deposit the spacer dielectric with a thickness greater than the target spacer thickness, anisotropically etched to expose the top of the fin. Ultimately, the new process makes it possible to remove the spacer from fin sidewalls without damaging the fin or BOX/Shallow Trench Isolation (STI) dielectric between the fins.

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FinFET spacer formation without fin damage

Forming gate spacer on FinField Effect Transistors (FinFET) is a challenge. To clear the spacer material from the fin sidewalls, the spacer dielectric must be overetched by a thickness at least equal to the fin height (and some overetch). The gate height needs to increase to make sure the spacer is still left on gate sidewalls, which leads to a higher gate-contact capacitance. It also leads to erosion of the fin from the top as well as a recess in the BOX/Shallow Trench Isolation (STI) dielectric between the fins. Typical numbers are 5-10nm loss of the fin. While this unintentional fin recess can be accounted for in an overall intentional fin recess used to form embedded stressors, it is difficult to control the uniformity of the unintentional fin recess caused by spacer Reactive Ion Etching (RIE).

The invented method does not pull down the spacer from fin sidewalls. The novel approach is to deposit the spacer dielectric with a thickness greater than the target spacer thickness, anisotropically etched to expose the top of the fin. The fin is then recessed in preparation of embedded stressor process. The remaining spacer dielectric is isotropically etched. On the fin sidewalls, the spacer is etched from both sides, while on the gate sidewalls it is etched from one side only. This makes it possible to remove the spacer from fin sidewalls without damaging the fin or BOX/STI.

For example, for a final spacer thickness of 6nm...