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Capping layer free damascene dummy gate formation for RMG finFET fabrication

IP.com Disclosure Number: IPCOM000235786D
Publication Date: 2014-Mar-25
Document File: 5 page(s) / 84K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a damascene dummy gate process for fabricating Replacement Metal Gate (RMG) fin Field Effect Transistor (finFET) devices, where a new sacrificial dummy gate material is introduced, which can be SiN in one embodiment. The process uses a damascene trench for a dummy gate formation patterned selectively against the Nominal Oxide/Thick Oxide (SG/EG) around fins.

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Capping layer free damascene dummy gate formation for RMG finFET fabrication
In the conventional gate scaling process, the dummy gate height becomes much taller in order to compensate for the process variation of the gate hard mask and work function recess uniformity. On the other hand, with a small gate length at tighter gate pitches, the dummy gate has an even higher aspect ratio, which increases the risk of pattern collapse or movement.

Almost all the existing methods use a line-first structure, and then form the gate trench structure later, where there are always tall gates with high aspect ratios. Thus, a re-entrant structure forms, with the potential for pattern collapse. The solution discussed herein is using a different flow; a dummy trench structure is formed at the very beginning, followed with easy control in hard mask and work function deposition and recess.

The novel contribution is a trench-first method for a damascene dummy gate process for fabricating Replacement Metal Gate (RMG) fin Field Effect Transistor (finFET) devices. This differs from the conventional line-first method in prior arts. The method comprises sacrificial dummy gate material, which is easily and selectively removed, and a damascene trench-first structure for gate formation. The trench-first method solves current issues by:


 Avoiding forming tall gate structure with high aspect ratios


 Improving the limited gate length due to high aspect ratios


 Avoiding gate pattern collapse


 Avoiding dummy gate re-entrant structure, hence reducing the voids and defectivity

The method comprises the following components and process:

1. Introduce a new sacrificial dummy gate material (e.g., Silicon Nitride (SiN))

2. Selectively pattern a damascene trench for dummy gate formation against the Nominal Oxide/Thick Oxide (SG/EG) around fins 3. Damascene the dummy gate into the already patterned trench (e.g., boron doped carbon film)

4. Selectively remove the sacrificial dummy gate material (SiN) from the source/drain region, against the EG/SG oxide, and hence minimize the fin erosion

  5. Perform SiN spacer dep-etch 6. Continue with fin epitaxial (EPI) merge and conventional Poly-Open Chemical Mechanical Planarization (POC) and RMG process
An RMG-friendly dummy gate profile is advantageous because there is no reentrant profile and it is easy for high-k dep and work function metal fill and re...