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Method and System for Fabricating a Partial and a Full Replacement Spacer for Replacement Metal Gate Devices

IP.com Disclosure Number: IPCOM000235793D
Publication Date: 2014-Mar-25
Document File: 4 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for fabricating a partial and a full replacement spacer for Replacement Metal Gate (RMG) devices. The method includes steps of fabricating the partial and the full replacement spacer for a semiconductor wafer.

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Method and System for Fabricating a Partial and a Full Replacement Spacer for Replacement Metal Gate Devices

Disclosed is a method and system for utilizing partial and full replacement spacer for RMG devices. Fig 1 illustrates a semiconductor substrate with a post spacer etch. Fig. 2 illustrates the step of depositing Tantalum Nitride (TaN). This step is performed when an ionic barrier is required due to a flowable oxide polish slurry. As shown in fig. 2, the black deposition on the substrate represents the TaN deposition.

Figure 1

Fig. 3 illustrates the step of depositing the flowable oxide. The blue color on the substrate represents the flowable oxide. Fig. 4 illustrates the step of depositing a Gap Fill Oxide (such as, but not limited to, flowable CVD Oxide). The series of black blocks on the flowable oxide in Fig. 4 represent Nitride Bump formed due Overlap between the nFET and the pFET boundaries. These Tall Nitride regions get revealed during the flowable oxide polish which stops selectively on Nitride.

Figure 2

Figure 3

In a subsequent step, a bump polish is performed on the wafer, as shown in fig. 5. Fig. 6 illustrates the step of performing a nitride etch in the wafer.

Figure 4

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Figure 5

Figure 6

In the next step, the flowable oxide layer is removed from the wafer, as shown in fig. 7. Fig. 8 illustrates the step of removing the TaN layer from the wafer.

Figure 7

Figure 8

Fig. 9 illustrates a step of depositing a Middle of Line (MOL) irad n...