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Novel Finfet fin merge process wiht non-selective CVD deposition technique

IP.com Disclosure Number: IPCOM000235795D
Publication Date: 2014-Mar-25
Document File: 6 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel Fin field effect transistor (Finfet) merge process with non-selective Chemical Vapor Deposition (CVD) technique that uses a non-selective a-Si dep/etch.

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Novel Finfet fin merge process wiht non -selective CVD deposition technique

Selective Epitaxial growth on Fin Field Effect Transistors (Finfet) is a challenge in terms of epitaxial (EPI) merge, defectivity, and height control. EPI grows readily on any defective sites or poly gate exposure during spacer etch. The quality of EPI is also quite poor, shows many dislocations, and increases the external resistance. a-Si provides an excellent gap fill between fins to merge and smooth the deposition profile.

One approach is to grow EPI that is not thin enough to merge and then have amorphous Si by Chemical Vapor Deposition (CVD) technique fill the gaps between fin. Anneal is used to merge EPI and aSi to form low resistance crystalline Si source and drain. a-Si can be doped with B or P to lower external resistance further. Merged fins with Si can be patterned with RX.

The novel contribution is a non-selective a-Si dep/etch. The solution is comprised of the following:


1. Grow partial EPI on fins to reduce Rext


2. Merge Fins with non-selective CVD a-Si deposition


3. Planarize Si and pattern Rx


4. Convert a-Si to poly with anneal

The solution provides an inexpensive process with no nodule growth or cut. Gap fill between fins are well known for gate Si deposition; not dependent on fin pitch. The solution provides the same S/D or Fin merge height across macros (various C preprocessors (CPPs)).

Figure 1: Perpendicular to PC

Figure 2: Perpendicular to fin

The process flow follows:


1. Post-Gate etch with fins

1


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2. Spacer process


3. EPI growth (no merge)

4....