Gated-Diode as a Semiconductor Production In-line Charging/Process Induced Damage Monitor
Publication Date: 2014-Mar-25
The IP.com Prior Art Database
A method of using a gated-diode structure to monitor for process induced charging damage is set forth. Historically, a FET or FET-like structure is used to monitor for process induced charging damage by measuring gate dielectric reliability, such as time dependent dielectric breakdown.
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Gated-Diode as a Semiconductor Production In -line Charging/Process Induced Damage Monitor
Historically, a FET or FET-like structure is used to monitor for process induced charging damage by measuring gate dielectric reliability characteristics such as time dependent dielectric breakdown (TDDB). Previous methods involved using a FET or FET-like structure and attaching a back-end antenna, which consists of large area metal lines and vias to collect charge during the back-end processing, Back-end processing involves plasma-based steps such as Reactive Ion Etching (RIE) or plasma assisted deposition. During these plasma-based steps, the metal lines and vias can collect charge, which is directed towards and through the gate oxide of the FET, thus damaging the gate oxide, and resulting in increased gate leakage or FET threshold voltage. Reference structures which have identical FET or FET-like structures, but minimum back-end wiring, to minimize process induced charging damage, are also included. Because this reference structure has minimum back-end wiring, the charging damage on these structures is minimized, and thus serves as a charging free reference device against which the antenna devices is compared. If the antenna devices have a degraded TDDB lifetime compared to the reference device, that indicates that the wafer has experienced charging damage during back-end processing.
In this article we disclose a method of using a gate-diode structure to monitor for process induced charging damage. A back-end antenna consisting of metal wires and vias is connected to the gate, anode and cathode of a gated-diode structure. During processing of the wafer, the metal wires and vias collect charge during the plasma-based process steps, and direct them into the gate, anode and cathode terminals of the gated-diode structure. If the charging damage from the back-end processing is severe, electrical characterization of the diode will reveal the damage as shown below.
Table 1: diode characteristics from a good chip site, x=9, y=7 which has little to no charging damage:
Table 2: diode characteristic from a bad chip site, x=7, y=7 which has significant
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The tables above compare typical gated-diode results of...