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Dual Patterning Scheme of Single Metal RMG Stack to lower Gate Resistance and Improve Reliability (NBTI & PBTI)

IP.com Disclosure Number: IPCOM000235813D
Publication Date: 2014-Mar-25
Document File: 3 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a scheme to enable an AO implementation for negative Field Effect Transistors (nFET) and keep the reliability cap Titanium Nitride (TiN) for positive Field Effect Transistors (pFET), in order to improve the reliability.

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Dual Patterning Scheme of Single Metal RMG Stack to lower Gate Resistance and Improve Reliability (NBTI & PBTI)

Sigma stack is an alternative approach for Replacement Metal Gate (RMG). The use of AO(La2O3) is a very good knob for positive Bias Temperature Instability (pBTI) reliability. Keeping the reliability cap Titanium Nitride (TiN) has a negative Bias Temperature Instability (nBTI) reliability.

However, using an AO implementation in the current process flow is problematic because of regrowth (1-1.5A). In addition, the current AO process flow is not compatible with keeping the reliability cap TiN. Therefore, the process cannot implement AO and keep the reliability cap TiN to improve both pBTI and nBTI.

The solution is a scheme to enable an AO implementation for negative Field Effect Transistors (nFET) and keep the reliability cap TiN for positive Field Effect Transistors (pFET), in order to improve the reliability. In addition, since cap TiN is kept for pFET, a thinner wetting TiN layer is needed to protect high-K (HK) for pFET. With this scheme, the total gate stack thickness for the nFET is thinner than process on record (POR); thus, it produces lower gate resistance.

The steps of the patterning process flow in a preferred embodiment are represented in the following figures.

Step 1: pFET cap TiN Patterning

Step 2: AO driving-in in nFET

1


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Step 3: Anneal to set up nFET work function for single TiN

Step 4: nFET first patterning to removal nFET ca...