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Address Mode Aware Branch Prediction With Shutdown Capability

IP.com Disclosure Number: IPCOM000235852D
Publication Date: 2014-Mar-27
Document File: 5 page(s) / 109K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a Branch Target Buffer (BTB) method applied to processor architectures that performs asynchronous, lookahead branch prediction from the main processor pipeline and begins with instruction fetching. The method enables the microprocessor to implement instructions for changing address mode in a way that provides good performance and minimizes complexity.

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Address Mode Aware Branch Prediction With Shutdown Capability

Processor architectures can support more than one addressing mode with different sized addresses. For example, known architecture supports 24-bit, 31-bit, and 64-bit address modes, where the sizes of the addresses are 24, 31, and 64 bits, respectively. Instructions are provided for setting the addressing mode as well as branch instructions that change the addressing mode.

Existing systems can predict address mode changing branches by accessing addressing mode prediction tables in parallel with instruction fetching, and then using the predicted address mode to affect the target address generation as well as subsequent sequential address generation. Existing systems can alternatively detect

when an address was generated in the wrong address mode, update the address mode, and repeat the address generation.

A method is needed that enables the microprocessor to implement these instructions for changing address mode in a way that provides good performance and minimizes complexity.

Branch prediction is a performance-critical component of a pipelined high frequency microprocessor. It is used to predict the direction (Taken vs. NotTaken) and the target address of each branch instruction. This is beneficial because it allows processing to continue along a branch's predicted path rather than having to wait for the outcome of the branch to be determined. A penalty is incurred if a branch is mis-predicted.

An asynchronous lookahead branch predictor that augments performance is also needed.

A Branch Target Buffer (BTB) is a structure that stores branch and target information. It is a cache of branch information and in many ways is analogous to instruction and data caches. Other structures, such as a Branch History Table (BHT), Pattern History Table (PHT), and Multiple Target Table (MTT), can be included to store additional information used for branch direction and target prediction.

For the purposes of this article, the description of the novel contribution assumes any such structures can be accessed in parallel with the BTB with the same latency as the BTB.

The novel contribution is a method to perform asynchronous, lookahead branch prediction from the main processor pipeline, which begins with instruction fetching. Upon being restarted at a specified instruction address at the same time as instruction fetching, branch prediction independently searches the BTB for the first branch at or after the restart address. Upon finding a branch, the branch prediction logic reports it to the instruction fetching logic and to the pipeline logic to allow eventual correlation between branch predictions and the instructions being decoded. Independently from the rest of the pipeline, the branch prediction logic re-indexes with the predicted target

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address of a predicted taken branch. For a predicted not-taken branch, it continues searching in a sequential manner. It then looks for t...